Layout review notes
All boards below pass DRC (zones refilled, error severity) against their own rules AND schematic-parity 0/0. These notes capture deviations from the default line template that a human should eyeboll before committing a fab order. This is not a defect list — it is the "know what you're ordering" list.
Design-rule relaxations#
| Board | Deviation | Why | Action before fab |
|---|---|---|---|
axs-043-eco2 | Board min clearance relaxed to 0.10 mm (default 0.15) | CCS811 ams LGA-10-1EP vendor pad geometry spaces the EP 0.1 mm from signal pads; routed spacing stays ≥0.2 mm | Confirm the chosen fab supports 0.1 mm (4 mil) min spacing, or hand-adjust the EP escape. Most JLCPCB/PCBWay processes do. |
Non-default board sizes (informational, not a concern)#
Several boards enlarged the 20×25 mm default to fit their parts — all normal: axs-001 (20×40, switch pack), axs-002 (24×25, reed length), axs-005 (24×42, EC11), axs-010 (46×42, MAX31865 + terminal), axs-026 (64×40, MAX9814 chain), axs-029 (20×80, stereo mic separation), axs-031 (48×46, MCP3008 + header), axs-036 (50×50, HX711 + load-cell terminal), axs-045 (40.5×42, dual power domain), axo-018 (34×52, DS3231 RTC + 20 mm Keystone 3034 coin-cell holder — the ~24 mm-wide holder courtyard plus clean routing channels drove the size), axo-017 (30×40, Hirose DM3AT microSD socket — the ~16×18 mm socket courtyard sits at the top with the card opening overhanging the top edge, and a two-row passive band below it feeds the six SD-spec pull-ups plus the two 100R series resistors and decoupling before the PMOD plug), axc-008 (60×48, USB-A THT horizontal receptacle on the top edge + 5.08 mm external-5V terminal block on the right edge — neither fits the 20×25 default; the isolated VBUS island and the D+/D- data path need the middle band). Confirm these still panelize acceptably for the shared fab order.
Socket-carrier boards (plug-in module, not fully SMT)#
Per the catalog's stock-assets rule, these carry a socket for a COTS module rather than the bare sensor: axs-021 (RCWL ultrasonic), axs-024 (TFmini-S), axs-025 (LD2410), axs-044 (PMS5003), axs-046 (GPS), axs-047 (RC522). Their BOM lists the socket; the plug-in module is a separate line item.
axl-008-breadboard (layout)#
Board frame is 30 x 38 mm at origin (105,100), larger than the 20 x 25 mm default: the adapter carries three connectors (a 2x06 PMOD plug plus two 1x06 breadboard rows) and eight 0603 series resistors, which do not fit the default outline. J2/J3 are deliberately stacked 7.62 mm (0.3") apart per the schematic's breadboard-DIP intent, aligned column-for-column with the J1 signal pads. All other design rules are stock (0.15 mm track/clearance, 0.6/0.3 vias, GND pours on both layers). J1 carries 3.3V logic only.
axl-003-wavegen (layout)#
Board frame is 60 x 46 mm at origin (100,100), larger than the 20 x 25 mm default: the board carries a 17-resistor R-2R ladder (8 legs + 7 chain + 1 terminator), an OPA356 buffer, two decoupling caps, a 1x02 output header and a panel BNC, which do not fit the default outline. The BNC (J3) is placed so its barrel/nut deliberately overhangs the right board edge toward the panel; its copper pads stay on-board. All other design rules are stock (0.15 mm track/clearance, 0.6/0.3 vias, GND pours on both layers). J1 carries 3.3V logic only (8 host-driven data bits D0-D7 + power/ground). D0-D3 are straight F.Cu verticals above the odd PMOD pads; D4-D7 rise through the inter-column gaps and fan out on B.Cu (no crossings). The LAD3->LAD4 bridge (R12) and the two ladder groups are joined on B.Cu; the analog output path (LAD7 -> OPA356 -> 100R -> BNC/header) is kept compact in the top-right.
axc-004-lora (layout)#
Board frame is 40 x 44 mm at origin (100,100), larger than the 20 x 25 mm default: the RFM95W (HOPERF SMD, ~16 mm body), the SPI/DIO series+pull-up network, the module decoupling and the antenna sub-circuit (JP1 route select, J2 u.FL, J3 wire pad) do not fit the default outline. J1 carries 3.3V logic only (SPI ~CS/MOSI/MISO/SCK + DIO0/DIO1 IRQs + ~RST + power/ground). The RFM95W is SMD (F.Cu pads only) so B.Cu is free under the module and is used for the SPI fan and LORA_DIO descents. GND pours on both layers, stock 0.15 mm track/clearance, 0.6/0.3 vias.
Deviations from stock rules:
- RF keep-out: a rule area over the antenna feed (JP1 split point and the ANT / ANT_UFL / ANT_PAD traces, rect (123.5,108)-(131,125), both layers) forbids zone fill only (tracks/vias/pads allowed) so no ground pour sits under the RF feed, per the schematic RF-keep-out note. J2/J3 sit just outside it so the GND pour still grounds the u.FL shield pads.
- RF feed traces are 0.4 mm but NOT impedance-controlled: this is a 2-layer board with no defined stackup, so the 50 ohm target from the schematic note is not met by geometry. A quarter-wave wire (J3) or a short u.FL pigtail (J2) is the intended antenna; the ~10 mm on-board feed is short relative to 915 MHz. Flagged for a stackup/impedance review before release.
- SolderMaskMinWidth set to 0: the stock u.FL footprint (U.FL_Hirose_U.FL-R-SMT-1_Vertical, J2) carries an internal F.Mask rectangle that sits within the default mask-min-width of its own signal pad, producing a footprint-internal solder_mask_bridge that is not a real board defect.