Roadmap

How the 94 module designs become fabricable boards, and what "production ready" means in this repo.

Definition of done (in-repo)#

A board is fab-ready when, verified by kicad-cli (not by README prose):

1. Schematic ERC-clean ✅ (all 94 already pass)
2. PCB laid out — a hand-written generate_pcb.py using pmod-common/sensor_pcb_lib.py, following the axs-007-sht31 template
3. DRC-clean — pcb drc --refill-zones --severity-error reports 0 violations and 0 unconnected pads
4. Fab package exported — gerbers, Excellon drill, CPL, BOM, upload zip, via tools/fab_export.sh

Stages 1–4 are everything the repo can prove. Physical readiness (fabricated, assembled, bench-tested) is deliberately out of scope here — it needs a real fab order and bench, and is tracked as a separate milestone.

Tooling (all repeatable)#

• tools/gen_status.sh — regenerates STATUS.md from live kicad-cli output.
• tools/fab_export.sh <dir>|--all — DRC-gates a board, then emits its fab package. Exit status = number of boards that failed the gate.
• tools/LAYOUT_AGENT_PLAYBOOK.md — the exact recipe for authoring one board's layout (used by layout agents and humans alike).

The bottleneck#

93 of 94 modules need a PCB layout. This is real per-board engineering (deliberate placement + 2-layer manual routing + GND pours), done and DRC-gated one board at a time — not autorouted, not mass-generated blindly. Layout is produced in waves, each wave DRC-verified before the next.

Wave plan#

• Wave 0 — infrastructure (done): reference board axs-007 DRC-clean and fab-packaged; pipeline + status tooling proven.
• Wave 1 — pilot batch (in progress): the six one-per-protocol-class boards from the sensor-line plan — axs-001 (GPIO), axs-006 (1-Wire), axs-007 (I2C, done), axs-016 (SPI), axs-021 (pulse), axs-046 (UART), plus axs-034 (I2C power). Shakes out the template across every interface class. Panelize together for the first physical fab order.
• Wave 2 — I2C/SPI/UART fill: the bulk of the sensor line + simple I/O boards (LED bar, 7-seg, buzzer, RTC) — near-copy of wave-1 patterns.
• Wave 3 — actuator + power: drive modules, then battery-power-input and robot-power-dist (wider copper, thermal relief — different rules).
• Wave 4 — flagships: camera, VGA, Ethernet PHY, BLDC. These are gated on the ECP5 rev-A host decisions in BACKLOG.md (dual-row PMOD spacing, clock-capable pins) — do not lay out until those freeze.

Parallel HDL track (no fab cost)#

Shared cores in pmod-common/hdl/ already cover i2c/spi/uart/1-wire/pulse/ pwm/servo/quad/i2s/ws2812/seg7/debounce with testbenches. Per-board work is a top-level demo + pin map. This proceeds independently of layout.

Physical milestone (separate, needs spend)#

Once wave 1 is fab-ready: panelize the 6–8 boards, order one cheap JLCPCB/PCBWay run (~$30–60 + assembly), and bench-bring-up one board end to end. This verifies the single highest-risk unknown — the PMOD pin-1 corner vs. the ECP5 host socket — which, if wrong, invalidates all 94 footprints at once. Nothing else should be fabbed before that check passes.