← AXA-002

Circuit review & bench-test guide

AXA-002 — DRV8871 high-current DC motor driver PMOD module

Document purpose#

This document explains the axa-002-hc-motor PMOD module at component level and turns the design intent into a practical manual-review and bench-test plan. It is based on the schematic generator (generate_design.py), the module README, and the actuator-line rules in ../README.md, cross-checked against the TI DRV8871 datasheet (SLVSCY9B).

This is an unfabricated prototype design. The schematic is generated and ERC-clean (0/0) and the netlist has been reviewed, but no PCB layout exists, no board has been built, and no bench evidence of any kind exists. Every number below is a design target derived from the schematic and the datasheet, not a measurement. Nothing in this document proves that an assembled board is safe, thermally adequate, or conforming; that is what the bench procedure in section 9 is for, once a board exists.

1. What the board does#

The board is a single-channel brushed-DC motor driver PMOD module: catalog entry #2 (level L2) in the AruviX actuator line. A TI DRV8871 integrated H-bridge (four N-channel MOSFETs, 3.6 A peak, 6.5–45 V) drives one motor from the IN1/IN2 logic pair on PMOD pins 1 and 2. The lesson this module adds over AXA-001 (TB6612) is hardware current regulation: a single resistor (R1) programs a cycle-by-cycle current-chopping threshold, so a stalled motor draws a bounded, resistor-defined current instead of its raw stall current.

Motor power (VM, 6.5–45 V) enters only on the J2 screw terminal and never touches the PMOD connector; the PMOD carries 3.3 V logic and ground only. Grounds join on this module. The module targets JGA25-class geared DC motors.

It has no fault output and no status LED: the DRV8871 has no fault pin (a documented exception to the actuator-line feedback rule), so the host cannot observe UVLO, overcurrent, current-limit chopping, or thermal shutdown electrically. A motor that spins proves only that one direction of the bridge works at that load; it does not prove the current limit value, the other three truth-table states, thermal capability, or UVLO behavior.

Functional block diagram#

PMOD host (FPGA, 3.3 V logic)          Motor supply 6.5-45 V
        │                                      │
        v                                      v
J1 PMOD plug ── IN1 (pin 1) ──┐        J2 screw terminal
   3V3: pins 6, 12 (unused    │           │ VMOT     │ GND
   by U1 - logic ref only)    │           ├── C1 10 µF ─┐
   GND: pins 5, 11 ───────┐   │           ├── C2 10 µF ─┤
                          │   │           ├── C3 100 nF ┤
             IN2 (pin 2) ─┼─┐ │           v             │
                          │ │ └──> IN1  ┌─────────────┐ │
                          │ └────> IN2  │  U1 DRV8871 │ │
                          │             │  H-bridge + │ │
        R1 30.9 kΩ ──────────── ILIM ──>│  cycle-by-  │ │
        (I_TRIP = 2.07 A) │             │  cycle ILIM │ │
                          │             └──┬───────┬──┘ │
                          │           OUT1 │       │ OUT2
                          │                v       v    │
                          └── GND       J3 MOTOR terminal
                       (joins here)     (to brushed DC motor)

2. Safety and scope boundaries — actuator-specific#

This board drives motors: moving, energy-storing, inductive loads. The rules below are not optional style; each one exists because the failure it prevents is fast and physical.

• First power-up is always on a current-limited bench supply on the motor rail. Set the current limit below the expected first-test demand (start at 0.2–0.3 A with no motor, raise deliberately). Never use an unlimited battery or high-current brick for first power-up.
• Know the stall current of the motor before connecting it. Typical vendor-listing values (estimates, not citations — verify against the specific motor's datasheet): N20-class micro gearmotors stall at roughly 0.36–1.6 A depending on winding; JGA25-class geared motors, which this board targets, can stall at up to about 4 A at 12 V. Both exceed or approach the 2.07 A I_TRIP and the DRV8871's 3.6 A peak rating; the current-limit test in section 9.E exists precisely because stall is the normal worst case for a geared motor, not a fault.
• Never hot-plug or hot-unplug motor leads while the board is powered. Breaking an inductive circuit under current produces a flyback arc at the screw terminal and an uncontrolled voltage spike; making it can bounce. Power down, wait, connect, verify, then power up.
• External rail sequencing: logic before motor. Bring the 3.3 V logic rail (and the host's IN1/IN2 drive, held at 00) up before the motor rail, and take the motor rail down before logic. The DRV8871 datasheet permits input pins to be powered before VM, and its internal 100 kΩ pulldowns default the inputs to coast — but floating or powered-down host outputs are not a defined state to rely on while 45 V is on VM.
• Hands clear for the first commanded spin. Before the first IN1/IN2 command with a motor attached: motor mechanically secured (clamped or held in a fixture, never hand-held), nothing attached to the shaft, loose wires and fingers clear of the shaft and coupler, and one hand on the supply's output-off switch. Announce "spinning" if anyone else is at the bench. A geared output shaft has real torque even from a small motor.
• Flyback path verification is a test item, not an assumption. The design relies on the H-bridge body diodes (Vf 0.8 V typ, 1 V max at 1 A) plus C1/C2/C3 to absorb inductive kick. Section 9.E verifies that OUT1/ OUT2 and VMOT excursions stay inside the DRV8871 absolute maxima (OUTx: −0.7 V to VM + 0.7 V; VM: 50 V) during chopping and abrupt stop. Do not run near VM = 45 V until this is measured; kick headroom at 45 V is only 5 V to the VM absolute maximum.
• The 6.5 V minimum is real: DRV8871 UVLO disables the bridge below about 6.1–6.4 V. The module will not run from a 5 V USB brick, by design.
• Respect the connectors: the MKDS 1,5-class screw terminal and 2-layer 0603-passives board are appropriate for the ~2 A regulated regime, not for sustained multi-amp abuse. TI rates the DRV8871 at 2 A RMS at 25 °C on standard FR-4; treat that as the continuous ceiling until the actual layout's thermal behavior is measured.
• An earth-referenced oscilloscope ground clips only to board GND. OUT1 and OUT2 are switching nodes, never grounds.

3. Power and control behavior#

1. With VM present and IN1 = IN2 = 0 for more than t_SLEEP (1–1.5 ms), U1 is in low-power sleep: outputs High-Z, VM sleep current 10 µA max. The internal 100 kΩ pulldowns hold undriven inputs low, so an unconnected PMOD defaults to sleep/coast.
2. Raising IN1 or IN2 wakes the device; it is operational t_ON (40–50 µs) later. Truth table: 10 forward (current OUT1→OUT2), 01 reverse, 11 brake (both low-side FETs, slow decay), 00 coast/High-Z.
3. Speed control is PWM on one input while the other is static; TI recommends switching between drive and brake (slow decay). Input pulses must be at least 800 ns wide; usable PWM is 0–200 kHz (0–100 kHz per the overview text; stay at a few kHz to tens of kHz for this module).
4. Current regulation: U1 senses winding current internally. When it reaches I_TRIP = 64 kV / R_ILIM = 64 / 30.9 = 2.07 A, the bridge switches to slow decay (both low-side FETs on) for t_OFF (25 µs typ), then re-enables per IN1/IN2. A 2 µs blanking time (t_BLANK) ignores the switching spike. This repeats every cycle — it is a chopping regulator, not a latching fault, so a stalled motor sits at a bounded average current indefinitely (thermal limits permitting).
5. Independent protections: UVLO (VM falling 6.1–6.4 V, rising recovery 6.3–6.5 V, 100–180 mV hysteresis), overcurrent hard fault at I_OCP 3.7–6.4 A (deglitch 1.5 µs, auto-retry after 3 ms), and thermal shutdown at 150–175 °C with 40 °C hysteresis. All auto-recover; none is reported to the host.

Why current limit is the point of this module#

AXA-001's TB6612 has no current regulation: its stall protection is hope and thermal shutdown. On this module the stall current is set by R1, not by the motor winding. But note what I_TRIP does not do: it does not reduce average power dissipation to zero (the bridge still conducts ~2 A through ~565 mΩ total, ~2.4 W at stall before chopping duty is considered), and it does not protect the motor winding from sitting at 2 A. Stall tests are short, deliberate, and monitored.

4. Interfaces and reference designators#

There are no test points, LEDs, or fault lines in the current schematic. Probing is at the screw-terminal lugs, the R1/ILIM pad, and U1 pins. If a first-article layout can afford them, GND/VMOT/OUT1/OUT2 test loops are worth adding before fabrication.

5. Component-by-component review#

Every reference designator in generate_design.py is covered. #FLG01– #FLG03 are schematic-only ERC power flags on 3V3, GND, and VMOT; they place no parts and are not reviewed further.

5.1 Driver and connectors#

5.2 Current-limit programming and decoupling#

6. Datasheet summary and design interpretation#

Source: DRV8871 datasheet (SLVSCY9B, Rev. B) and the DRV8871 product page. Values below were read from that datasheet revision; check the current revision before procurement.

Not fetched / must be checked against datasheets before release: the exact Phoenix screw-terminal MPN and its current/voltage rating (generator marks it TBD), Murata capacitor DC-bias curves for the exact MPNs (the "well under half" derating statement above is a general X7R expectation, not a fetched curve), and the specific motor's stall current and winding resistance.

7. Expected values before bench testing#

All are design targets; none has been measured on hardware.

8. Manual schematic and assembly review checklist#

• Verify U1 pin-1 orientation against the DDA pinout (GND 1, IN2 2, IN1 3, ILIM 4, VM 5, OUT1 6, PGND 7, OUT2 8, thermal pad to GND).
• Inspect the PowerPAD joint (X-ray or at least edge-fillet inspection) — it is both the thermal path and a ground connection.
• Measure R1 = 30.9 kΩ on the ILIM net before any power is applied. A wrong reel here silently changes the board's headline safety number.
• Confirm C1/C2/C3 are the 50 V parts (1210/1210/0603), not lower-voltage lookalikes.
• Confirm J2 polarity marking on silkscreen matches the net assignment (pin 1 VMOT, pin 2 GND) and that J3 is labeled OUT1/OUT2.
• Confirm PMOD pin map: 1 IN1, 2 IN2, 5/11 GND, 6/12 3V3, all others NC — and that nothing else was accidentally routed to pins 3, 4, 7–10.
• Confirm there is no copper path from VMOT to 3V3 anywhere (ohmmeter: VMOT–3V3 must be open).
• When layout exists: verify PowerPAD thermal via field, VM decoupling placement adjacent to pin 5, and OUT1/OUT2 trace width for ≥ 2 A.

9. Ordered bench-test procedure#

Stop at the first abnormal result; diagnose before continuing. Record board serial, supply and meter IDs, ambient temperature, motor identity, and operator for every step. Two bench contexts are covered; run A–E standalone first, then F on the FPGA host.

Standalone context: logic 3.3 V from a lab supply (current-limited to ~100 mA) to J1 pins 6/12 and GND to 5/11; IN1/IN2 driven from a function generator or jumpers referenced to that same GND. Motor rail from a separate current-limited supply on J2. Grounds are joined on the module via J2 pin 2 and J1 pins 5/11 — do not add a second external ground bond between the two supplies at the bench, or motor return current can flow through the thin logic wiring; let the module's join be the single point.

PMOD host context: the FPGA board supplies 3.3 V and IN1/IN2 through J1; the motor supply still comes from its own current-limited source on J2. The motor return current path to that supply is J2 GND — but a soldering or layout fault could route it through the PMOD ground pins and the host FPGA board, so the first loaded test on a host is done at low current while watching for host brownout or hot PMOD pins. Sequencing in both contexts: host/logic up first with IN1 = IN2 = 0, then motor rail; motor rail off first at shutdown.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. DMM: VMOT–GND in both polarities (no hard short; expect capacitor charging behavior then high resistance), 3V3–GND (open on this module — 3V3 connects to nothing but the flags), VMOT–3V3 (open), OUT1–GND, OUT2–GND, OUT1–OUT2 (no hard shorts; body-diode drops in one polarity are normal).
3. Measure R1: 30.9 kΩ ± 1 % from ILIM to GND.
4. No motor connected. Screw terminals torqued on bare test leads only.

B. First power-up, no motor#

1. Logic context up (3.3 V, IN1 = IN2 = 0 or open — pulldowns hold low).
2. Motor supply: set 12 V, current limit 0.2 A, output off. Connect to J2 observing polarity. Enable output.
3. Expect: no current-limit trip; supply current falls to the µA range (sleep) within ~2 ms. Sustained mA-level draw with inputs low, or any current-limit trip, is abnormal — stop.
4. Drive IN1 = 1, IN2 = 0. Supply current rises to single-digit mA. OUT1 reads ≈ VM, OUT2 ≈ 0 V. Reverse the inputs and confirm the mirror. Drive 11 and confirm both outputs ≈ 0 V (brake). Return to 00 and confirm High-Z and re-entry to sleep.
5. Repeat step 4 at VM = 7 V and VM = 24 V (raise the current limit only as needed). Do not go above 24 V until section E's flyback results exist.

C. PWM and logic timing, no motor#

1. Apply 20 kHz PWM (50 %) to IN1 with IN2 = 0. Scope OUT1: clean switching between ≈ VM and 0 V, propagation delay ~0.7–1 µs, dead-time notches of ~220 ns are normal.
2. Verify narrow pulses: below 800 ns input pulse width, edges may be dropped per datasheet — confirm the host HDL never emits shorter pulses.
3. Confirm wake timing: from sleep (00 held > 1.5 ms), first output activity appears 40–50 µs after an input rises.

D. UVLO verification (board-specific, mandatory)#

1. No motor. Static drive 10 so OUTx state is observable. Motor-supply current limit 0.2 A.
2. Sweep VM slowly downward from 8.0 V while watching OUT1. Record the VM at which OUT1 collapses (outputs disabled): expect 6.1–6.4 V.
3. Sweep slowly upward and record where OUT1 re-asserts: expect 6.3–6.5 V, i.e. 100–180 mV above the falling threshold.
4. Values outside these windows, or chattering wider than the hysteresis band (check supply lead drop under the small load), are abnormal — stop.

E. Current limit and flyback (board-specific, mandatory)#

The DRV8871's regulation is cycle-by-cycle: at stall the current waveform is a sawtooth — current ramps up (di/dt set by VM and winding inductance), touches I_TRIP, then decays in slow-decay (both low-side FETs) for t_OFF ≈ 25 µs, and repeats. Expect the peaks to sit at ≈ 2.07 A (acceptance 1.89–2.26 A) with the 2 µs blanking spike at each re-enable. A flat DC current at stall, or peaks walking past 2.3 A, is abnormal.

1. Preferred method: current probe around one motor lead. Alternatives if no probe: (a) insert a low-side shunt (e.g. 50 mΩ, ≥ 2 W, low inductance) in the motor return between J3 and the motor and scope across it, or (b) locked-rotor with the bench supply's current limit set above 2.3 A and its ammeter watched — this shows only the average, not the sawtooth, so use it as a coarse check, not the acceptance measurement.
2. Set VM = 12 V, supply limit 3 A. Motor mechanically secured, shaft free, hands clear. Command a short forward burst (< 1 s) and capture start-up inrush: current should ramp to I_TRIP and chop during spin-up, then fall to run current.
3. Locked rotor: clamp the gearbox output (never fingers), command forward for ≤ 5 s while capturing the current waveform. Verify sawtooth peaks in the 1.89–2.26 A window and ~25 µs decay intervals. Monitor U1 temperature; abort if it climbs past ~100 °C case.
4. Flyback: with the scope on OUT1 (and then VMOT at J2), capture the instant of a drive-to-coast (10→00) transition under load and the chopping transitions. OUTx must stay within one body-diode drop of the rails (−0.7 V to VM + 0.7 V); VMOT ringing must stay well below 50 V. Repeat at 24 V before ever operating higher.
5. Only after 1–4 pass: repeat the stall capture at the highest VM you intend to use with the target JGA25-class motor.

F. PMOD host integration#

1. With the module proven standalone, power down everything, plug the module into the FPGA host PMOD (never insert or remove a PMOD live), motor supply still separate and current-limited.
2. Bring up host (IN1/IN2 driven 00 from HDL reset), then motor rail.
3. Run the HDL demo (pwm_gen + direction controller) through forward / reverse / brake / coast at low duty first. Watch host 3.3 V for droop and PMOD region for heating during motor load — evidence of a wrong ground return path.
4. Repeat a brief stall at 12 V in-system; confirm the host logic is undisturbed by the chopping (ground bounce check).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is small and coherent: one integrated H-bridge, one programming resistor, three decoupling capacitors, and a strict power topology in which motor current never crosses the PMOD connector. The safety architecture rests almost entirely on the DRV8871's internal features — cycle-by-cycle current regulation set by R1 (2.07 A nominal, 1.89–2.26 A with tolerances), UVLO, OCP, and TSD — plus the body diodes as the only flyback path.

The principal open risks, in order: (1) nothing has been fabricated or measured — every number above is a target; (2) the module is deliberately blind — no fault pin, no telemetry — so the host cannot distinguish TSD cycling from a mechanical jam, and the curriculum should say so; (3) an open R1/ILIM fault is not characterized in the datasheet and must be treated as loss of current limiting; (4) bulk capacitance (2 × 10 µF X7R, heavily derated at high VM bias) is modest against TI's 47 µF example — flyback and VM-ringing measurements at 24 V and above will decide whether the BOM needs a bulk electrolytic; (5) the PowerPAD thermal path is the make-or-break layout item for the not-yet-started PCB; and (6) the screw-terminal MPN is still TBD and its current rating unverified. None of these blocks the schematic; all of them gate release.