Sensor modules

AXS-036 — HX711 load cell ADC PMOD module

Catalog #36 in the AruviX sensor line, level L2 (bit-bang timing). The ubiquitous HX711 24-bit sigma-delta bridge ADC, with a Phoenix terminal block for a 4-wire load cell.

Level L2 ERC clean DRC clean Fab package 10 components

3D render of the AXS-036 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Band-gap reference bypass	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	100nF 16V X7R	AVDD high-frequency decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C3`	10uF 10V X5R	AVDD bulk decoupling (analog side, per datasheet)	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`C4`	100nF 16V X7R	DVDD/VSUP decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	LOAD CELL	Load cell terminal: 1 E+ (red), 2 E- (black), 3 A+ (green), 4 A- (white)	`MKDS 1,5/4-5,08 (1715048)` Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-4-5.08_1x04_P5.08mm_Horizontal`
`JP1`	RATE 10/80Hz	HX711 RATE strap: 1-2 GND 10 Hz (default), 2-3 DVDD 80 Hz	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`R1`	100R	Series protection on the sensor-driven DOUT line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	10k	PD_SCK pull-down: an unconfigured host must not float the part into power-down	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	HX711	24-bit sigma-delta ADC for weigh scales, 2-wire interface	`HX711` Avia Semiconductor Datasheet ↗	`SOIC-16_3.9x9.9mm_P1.27mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 DOUT GND HX_DOUT PD_SCK RATE SIG_M SIG_P VBG

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-036-hx711

Catalog #36 in the AruviX sensor line (../README.md), level L2 (bit-bang timing). The ubiquitous HX711 24-bit sigma-delta bridge ADC, with a Phoenix terminal block for a 4-wire load cell.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

A protocol that is neither SPI nor I2C — just two wires and timing rules:

Data-ready is signalled by DOUT falling while PD_SCK is low (poll it).
The host then bit-bangs 25, 26 or 27 PD_SCK pulses: 24 data bits MSB first, and the total clock count selects the next conversion's input and gain (25 = ch A ×128, 26 = ch B ×32, 27 = ch A ×64).
PD_SCK held high longer than 60 µs powers the chip down — a great "your pulse widths matter" lesson for an FSM with a cycle counter.

Design#

HX711 (Avia, SOIC-16) in the datasheet 3.3 V no-external-regulator configuration: VSUP = AVDD = DVDD = 3V3, VFB to GND, BASE open, so the load-cell excitation is the 3V3 rail (ratiometric — the bridge and the reference track).
VBG bypassed with 100 nF; AVDD gets 100 nF + 10 µF bulk, DVDD 100 nF.
XI to GND selects the internal oscillator; XO open.
RATE strap JP1: 1-2 = GND = 10 Hz (default), 2-3 = DVDD = 80 Hz.
Channel A only; unused INB+/INB− grounded.
J2 = Phoenix MKDS 1,5/4-5,08 terminal: E+ (red), E− (black), A+ (green), A− (white) — standard 4-wire load-cell colors.
Sensor-driven DOUT passes 100 Ω; PD_SCK has a 10 k pull-down so an unconfigured host cannot float the part into power-down.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	DOUT	PD_SCK	NC	NC	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (keep INA± routing short/symmetric, analog pour), DRC, fab
[ ] hdl/: HX711 bit-bang FSM with tare + scale, ECP5 demo
[ ] BOM export and availability check (HX711 sourcing), design review