Actuator modules

AXA-004 — Discrete H-bridge lab PMOD module

Catalog #4 in the AruviX actuator line, level L4. Four discrete FETs, no driver IC, no interlock: the FPGA drives all four gate signals and the fabric must guarantee dead time.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 GND HG1 HG1_PD HG2 HG2_PD HS1 HS2 IG1 IG2 LG1 LG2 LS1 LS2 OUT1 OUT2 VMOT

Production status#

Source: boards/actuator-modules/axa-004-hbridge-lab

Catalog #4 in the AruviX actuator line (../README.md), level L4. Four discrete FETs, no driver IC, no interlock: the FPGA drives all four gate signals and the fabric must guarantee dead time.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

SHOOT-THROUGH IS PHYSICALLY POSSIBLE BY DESIGN. Driving HSx and LSx high together shorts VM to GND through both FETs of that leg. That is the point of the module: deadtime_gen plus a self-checking testbench must prove no overlap before a motor (or a fuse) is attached. There is no silicon safety net — exactly the honesty every integrated driver hides.

What it teaches#

Dead-time insertion the honest way: gate-drive levels, asymmetric propagation paths, body-diode conduction during dead time, and formal-ish testbench proof obligations. This is the L4 counterpart of AXA-001/002 — same H-bridge truth table, but every failure mode is yours.

Topology (think it through before powering)#

Per half-bridge (channel x = 1, 2):

• Low side: AO3400A N-FET, gate driven directly from PMOD LSx through 100 Ω. Logic-level FET, fully enhanced at 3.3 V. LSx = 1 → low side ON.
• High side: AO3401A P-FET, source at VM. A 3.3 V PMOD pin cannot swing a gate that lives near VM, so PMOD HSx (through 100 Ω) drives a small AO3400A level-inverter whose drain pulls the P-FET gate down through 10 kΩ, against a 10 kΩ pull-up to VM:
• Inverter OFF → gate = VM → V_SG = 0 → high side OFF.
• Inverter ON → the 10k/10k divider parks the gate at VM/2 → V_SG = VM/2 → high side ON. The inverter cancels the inversion: HSx = 1 → high side ON. All four PMOD signals are active-high.
• Gate-rating math (why VM is 5–12 V): V_SG = VM/2 is 6 V at VM = 12 V — inside the AO3401A ±12 V absolute maximum with 2× margin — and 2.5 V at VM = 5 V, the AO3401A's specified enhancement point (R_DS(on) rated at V_GS = −2.5 V). Below 5 V the high side barely turns on; above 12 V the divider erodes the gate-rating margin. VM range: 5–12 V.
• Timing asymmetry: the high-side path has an extra FET stage plus the 10k/10k RC into the P-FET gate, so it switches slower than the direct low-side path. Your dead time must cover the measured asymmetry — scope both gates; that measurement is part of the lab.
• Idle safety: 10 k pull-downs on all four PMOD nets — an unpowered or unconfigured host leaves all four FETs off.
• Flyback: FET body diodes only (documented per the line rule). During dead time the motor current freewheels through them — watch the diode drop appear on the scope, then shorten (not eliminate!) the dead time.

Design#

• 2× AO3401A (−30 V, −4 A) high side, 4× AO3400A (30 V, 5.7 A) low side + inverters, all SOT-23.
• Motor power VM on J2 screw terminal only, never through the PMOD; bulk 2× 10 µF 25 V 0805 + 100 nF 50 V at the bridge. Grounds join on the module.
• Bridge output OUT1/OUT2 → J3 screw terminal.
• All PMOD lines host-driven → no 100 Ω module-driven series rule; no fault or sense line exists (documented exception: the module is deliberately dumb — pair it with AXA-003 or a shunt lab for feedback).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (20 × 40 mm actuator outline, tight bridge loop), DRC, fab outputs
• [ ] hdl/: deadtime_gen + bridge sequencer, self-checking no-overlap testbench (the release gate), ECP5 demo
• [ ] BOM export and availability check, design-review checklist