Sensor modules

AXS-037 — Force sensitive resistor PMOD module

Catalog #37 in the AruviX sensor line, level L3 (analog acquisition + calibration). An FSR divider through an anti-alias RC into an ADS7042 12-bit 1 MSPS SPI ADC — same acquisition pattern as AXS-030.

Level L3 ERC clean DRC clean Fab package 10 components

3D render of the AXS-037 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	10nF 50V C0G	Anti-alias RC capacitor and SAR charge reservoir	`GRM1885C1H103JA01D` Murata	`C_0603_1608Metric`
`C2`	100nF 16V X7R	AVDD/DVDD high-frequency decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C3`	1uF 10V X7R	AVDD/DVDD bulk decoupling	`GRM188R71A105KA61D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	FSR TERMINAL	FSR terminal: 1 = 3V3, 2 = divider node (FSR polarity does not matter)	not selected generic	`PinHeader_1x02_P2.54mm_Vertical`
`R1`	10k 1%	Divider lower leg: sets the force-to-voltage curve	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	1k	Anti-alias RC series resistor / SAR input isolation	`RC0603FR-071KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Series protection on the ADC-driven data line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	10k	~CS idle pull-up so the output stays released until the host selects it	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	ADS7042	12-bit 1 MSPS SAR ADC, SPI-compatible cs-framed interface	`ADS7042IDCUR` Texas Instruments Datasheet ↗	`VSSOP-8_2.3x2mm_P0.5mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADC_IN ADC_SDO CS_N FSR_NODE GND MISO SCK

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-037-fsr

Catalog #37 in the AruviX sensor line (../README.md), level L3 (analog acquisition + calibration). An FSR divider through an anti-alias RC into an ADS7042 12-bit 1 MSPS SPI ADC — same acquisition pattern as AXS-030.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Nonlinear sensor calibration. An FSR is >1 MΩ untouched and a few kΩ under a hard press, and its resistance-vs-force law is roughly a power curve, so the divider output is deliberately not linear in force. The lesson: capture a calibration data set with known weights, fit the force curve (log-log fit or lookup table), and implement the correction in fabric or software. Also: part-to-part spread and drift — why FSRs are pressure indicators, not scales (contrast with AXS-036).

Design#

FSR attaches via J2 (1×2 header, value "FSR TERMINAL", MPN TBD — target Interlink FSR-402; polarity irrelevant). It sits between 3V3 and the divider node.
10 kΩ 1% lower leg: output rises with force, mid-range sensitivity around the FSR's ~10 kΩ region.
1 kΩ + 10 nF C0G anti-alias RC (fc ≈ 16 kHz) also serves as the SAR input charge reservoir.
ADS7042IDCUR (VSSOP-8), AVDD = DVDD = 3V3 (AVDD is the reference), AINM to GND, 100 nF + 1 µF decoupling.
cs-framed read-only interface (no MOSI); SDO passes 100 Ω; ~CS has a 10 k idle pull-up.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	~CS	NC	MISO	SCK	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout, DRC, fab outputs
[ ] hdl/: sampler FSM + calibration LUT, ECP5 demo
[ ] Pin the FSR MPN (Interlink FSR-402 vs Ohmite FSR01CE)
[ ] BOM export and availability check, design-review checklist