Comms modules

AXC-001 — W5500 SPI Ethernet PMOD module

Catalog #1 in the AruviX comms line, level L3 (SPI + INT). WIZnet W5500 offloaded TCP/IP controller + Hanrun HR911105A integrated-magnetics RJ45: a working web server in a weekend.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 3V3A ACT_LED_A ACT_LED_N CS_N EXRES1 GND INT_N LINK_LED_A LINK_LED_N MISO MOSI RCT RST_N RXN RXN_T RXP RXP_T SCK TCT TOCAP TXN TXP V1V2 W5500_INT_N W5500_MISO XI XO

Production status#

Source: boards/comms-modules/axc-001-ethernet-spi

Catalog #1 in the AruviX comms line (../README.md), level L3 (SPI + INT). WIZnet W5500 offloaded TCP/IP controller + Hanrun HR911105A integrated-magnetics RJ45: a working web server in a weekend.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

An SPI master against a real peripheral protocol (variable-length frames, socket registers), interrupt-driven networking via ~INT, and the first half of the line's paired lesson — AXC-002 (LAN8720A) rebuilds the MAC in fabric behind the same upper-layer HDL/AruviOS interfaces (spi_w5500 driver + socket API shim in pmod-common/hdl).

Design#

• Analog front end copied from the WIZnet W5500-Ref-RJ45WithMag reference schematic: 49.9 Ω 1% pull-ups to 3V3A on TX±, TX center tap fed through 10 Ω with 22 nF decoupling, RX± AC-terminated 49.9 Ω + 6.8 nF, RX center tap 10 nF to GND.
• EXRES1: exact-value 12.4 kΩ 1 % bias to GND (datasheet requirement).
• 25 MHz crystal (CL = 12 pF, ABM8 class, MPN TBD): load caps C = 2 × (CL − Cstray) = 2 × (12 − 3) pF = 18 pF each + 1 MΩ feedback, matching the reference design.
• TOCAP 4.7 µF, 1V2OUT 10 nF, VBG floating, RSVD pins (23, 38–42) tied to GND — all per datasheet. PMODE straps left open: internal pull-ups give PMODE=111 (all-capable auto-negotiation), as in the reference schematic.
• 3V3 → 3V3A through a 120 Ω ferrite bead; 5 × 100 nF + 2 × 10 µF.
• Jack LEDs verified against the HR911105A datasheet (green anode 9 / cathode 10, yellow anode 12 / cathode 11) and driven by W5500 LINKLED/ACTLED through 330 Ω from 3V3. Jack pin 8 (Bob Smith chassis return) and shell tied to module GND; a 1 nF/2 kV chassis split is a layout decision.
• MISO and ~INT pass 100 Ω series resistors; ~INT (open-drain) and ~RST carry 10 k pull-ups on-module.

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (RJ45 hangs off the far edge; keep magnetics termination tight; >25 mil PMOD-clip clearance), DRC, fab outputs
• [ ] Pin the crystal MPN (ABM8-25.000MHZ class, CL = 12 pF)
• [ ] hdl/: spi_w5500 driver + socket API shim, testbench, ECP5 demo
• [ ] BOM export and availability check, design-review checklist