Sensor modules

AXS-040 — Capacitive soil-moisture carrier PMOD module

Catalog #40 in the AruviX sensor line, level L3 (SPI ADC readout of an analog probe).

Level L3 ERC clean DRC clean Fab package 10 components

3D render of the AXS-040 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	ADS7042 AVDD/DVDD decoupling (place at the pins)	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	1uF 16V X5R	ADS7042 reference/bulk decoupling	`GRM188R61C105KA93D` Murata	`C_0603_1608Metric`
`C3`	10nF 50V C0G	RC filter / charge reservoir at the ADC input	`GRM1885C1H103JA01D` Murata	`C_0603_1608Metric`
`C4`	100nF 16V X7R	Probe socket decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C5`	10uF 10V X5R	Probe socket bulk reservoir	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	SOIL PROBE SOCKET	Socket for a 3.3 V analog capacitive soil probe: 1 VCC, 2 GND, 3 AOUT	not selected generic	`PinSocket_1x03_P2.54mm_Vertical`
`R1`	1k	RC anti-alias / charge-bucket source resistor into the SAR input	`RC0603FR-071KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection on the ADC-driven data line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	ADS7042	12-bit 1 MSPS SAR ADC, SPI, AVDD as reference	`ADS7042IDCUR` Texas Instruments Datasheet ↗	`VSSOP-8_2.3x2mm_P0.5mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADC_CS_N ADC_SDO GND MISO SCK SOIL_AOUT SOIL_FILT

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-040-soil

Catalog #40 in the AruviX sensor line (../README.md), level L3 (SPI ADC readout of an analog probe).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Bridging the analog world with the smallest possible ADC. The capacitive soil probe outputs a slow analog voltage; an on-carrier ADS7042 (12-bit, SAR, SPI) digitizes it. The ADS7042 has no configuration registers at all: drop ~CS, clock 16 SCLKs, read 12 bits — the gentlest possible first analog-acquisition core, plus practical lessons in RC input filtering and averaging a noisy, slow-settling sensor.

Design#

J2 = 1×3 pin socket for a 3.3 V analog capacitive soil probe (v1.2 style): 1 VCC, 2 GND, 3 AOUT. Probe breakouts vary — check the order against your probe before plugging in, and use one specified for 3.3 V operation.
AOUT → RC 1k + 10 nF → ADS7042 AINP; AINM tied to GND (single-ended). The RC pair doubles as anti-alias filter and SAR charge reservoir.
100 Ω series on the ADC-driven SDO line.
ADC decoupling 100 nF + 1 µF at U1; 100 nF + 10 µF at the probe socket.
Full scale = AVDD = 3.3 V (the ADS7042 uses its supply as reference).
PMOD Type 2 SPI, read-only (no MOSI — pin 2 NC).

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	~CS	NC	MISO	SCK	GND	3V3	NC	NC	NC	NC	GND	3V3

Part choice: ADS7042IDCUR (VSSOP-8/DCU, stock KiCad symbol Analog_ADC:ADS7042xDCU and footprint Package_SO:VSSOP-8_2.3x2mm_P0.5mm).

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (keep the RC filter and ADC decoupling at the pins), DRC, fab
[ ] Verify probe VCC/GND/AOUT order against a purchased probe
[ ] hdl/: SPI master, ADS7042 frame unpack, moving-average filter, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist