Sensor modules

AXS-019 — LIS3MDL 3-axis magnetometer PMOD module

Catalog #19 in the AruviX sensor line, level L3 (I2C).

Level L3 ERC clean DRC clean Fab package 12 components

3D render of the AXS-019 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	C1 internal-regulator capacitor per datasheet	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	100nF 16V X7R	Vdd/Vdd_IO decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C3`	1uF 10V X7R	Module bulk decoupling	`GRM188R71A105KA61D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`JP1`	SDA PULL-UP	Cut to remove the SDA pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP2`	SCL PULL-UP	Cut to remove the SCL pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP3`	ADDR 0x1C/0x1E	I2C address select: 1-2 SA1 low 0x1C (default), 2-3 SA1 high 0x1E	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`R1`	4.7k	I2C SDA pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	4.7k	I2C SCL pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Series protection on the sensor-driven INT line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection on the sensor-driven DRDY line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	LIS3MDL	3-axis magnetometer, +/-4 to +/-16 gauss, I2C/SPI	`LIS3MDLTR` STMicroelectronics Datasheet ↗	`LGA-12_2x2mm_P0.5mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADDR C1_REG GND LIS_DRDY LIS_INT MAG_DRDY MAG_INT SCL SCL_PU SDA SDA_PU

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-019-lis3mdl

Catalog #19 in the AruviX sensor line (../README.md), level L3 (I2C).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

I2C against a field sensor with real-world calibration content: compass heading, hard/soft-iron calibration, and interrupt/data-ready handshaking (INT and DRDY are wired to the two spare PMOD pins).

Design#

LIS3MDLTR, LGA-12 2×2 mm. Vdd and Vdd_IO both on 3V3.
I2C mode is hard-wired: ~CS tied to 3V3, so SPI is not reachable on this board.
JP3 straps SDO/SA1: 1-2 (default) = GND = address 0x1C, 2-3 = VDD = 0x1E.
4.7 kΩ bus pull-ups behind JP1 (SDA) / JP2 (SCL), bridged by default — cut when another module on the chain provides the pull-ups.
Sensor-driven INT and DRDY pass through 100 Ω series resistors.
Capacitors: 100 nF on the C1 pin (the LIS3MDL internal-regulator capacitor required by the datasheet — not decoupling), 100 nF Vdd decoupling, 1 µF module bulk (GRM188R71A105KA61D).

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	MAG_INT	MAG_DRDY	SCL	SDA	GND	3V3	NC	NC	SCL	SDA	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (20 × 25 mm outline, keep the sensor away from the header current loop), DRC, fab outputs
[ ] hdl/: I2C master, LIS3MDL controller, heading/atan2 demo, testbench
[ ] BOM export and availability check, design-review checklist