← AXS-019

Circuit review & bench-test guide

AXS-019 — LIS3MDL 3-axis magnetometer PMOD module

Document purpose#

This document explains the axs-019-lis3mdl prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the manufacturer documents cited in Section 6.

The board is schematic-only: ERC is clean, but no PCB has been laid out and no board has been fabricated or assembled. There is no bench result of any kind. Every numeric value in this guide is a verification target taken from the design files or the manufacturer datasheets, not a measured result.

1. What the board does#

The board puts an STMicroelectronics LIS3MDL 3-axis magnetometer on the AruviX I2C PMOD template. A 3.3 V PMOD host talks I2C (address 0x1C by default, 0x1E via solder jumper JP3) to read X/Y/Z magnetic field at ±4/8/12/ 16 gauss full scale, for compass-heading and hard/soft-iron-calibration lessons. The sensor's INT and DRDY outputs are wired to the two spare PMOD top-row pins through 100 Ω series resistors. The I2C bus is repeated on PMOD pins 9/10 so modules can be daisy-chained; the on-module 4.7 kΩ pull-ups sit behind solder jumpers JP1/JP2 so exactly one module in a chain provides them.

SPI is not reachable: the LIS3MDL ~CS pin is hard-wired to 3V3, which per the datasheet selects and locks I2C mode.

Functional block diagram#

PMOD host (3.3 V)
      │
      v
J1 PMOD plug (2x06)
  1 MAG_INT   <── R3 100R ── LIS_INT  ──┐
  2 MAG_DRDY  <── R4 100R ── LIS_DRDY ──┤
  3/9  SCL    <──── JP2 ─── R2 4.7k ── 3V3   (SCL pull-up)
  4/10 SDA    <──── JP1 ─── R1 4.7k ── 3V3   (SDA pull-up)
  5/11 GND, 6/12 3V3                    │
      │                                 │
      v                                 │
   U1 LIS3MDL (LGA-12)  ────────────────┘
      Vdd, Vdd_IO = 3V3 (C2 100n, C3 1u)
      ~CS = 3V3 (I2C mode locked)
      SDO/SA1 = ADDR ── JP3: 1-2 GND = 0x1C (default), 2-3 3V3 = 0x1E
      C1 pin ── C1 100n ── GND (internal regulator cap, NOT decoupling)

2. Safety and scope boundaries#

• 3.3 V logic only. Power from a PMOD host or a current-limited bench supply set to 3.3 V; a 50 mA current limit is far above the sensor's worst-case draw and still protects a miswired prototype.
• Absolute maximums (datasheet Table 8): Vdd and Vdd_IO −0.3 to +4.8 V; any control pin −0.3 to Vdd_IO + 0.3 V. Never drive SDA/SCL/INT/DRDY from a 5 V host.
• The part is magnetically fragile in a way most parts are not: a magnetic disturbance field above 50 gauss starts to degrade the zero-gauss offset and the maximum exposed field is 1000 gauss. Keep strong magnets (and magnetized tools/tweezers) away except for the deliberate, brief proximity test in Section 9.F.
• Compass accuracy is corrupted by nearby current loops: ST recommends keeping traces carrying more than 10 mA a few millimeters away from the sensor. Route bench wiring accordingly and keep the module away from the supply leads during field tests.
• This guide validates a prototype schematic. Passing it is not EMC, safety, or environmental qualification, and no PCB-dependent behavior (layout coupling, thermal, soldering) can be checked before layout exists.

3. Power and control sequence#

1. 3V3 is applied on J1 pin 6/12. C3 (1 µF bulk) and C2 (100 nF) charge; the LIS3MDL internal regulator starts against C1 (100 nF on the C1 pin).
2. Per AN4602 Section 3.1, after power-on reset the device loads factory trim from internal flash, performs one measurement, and enters idle (power-down) in about 3.2 ms. DRDY is low during startup.
3. Default register state: CTRL_REG1 = 0x10, CTRL_REG3 = 0x03 (power-down). Idle current is about 1 µA, so the module at rest should draw only microamps plus pull-up leakage.
4. The host configures full scale (CTRL_REG2, 0x21), operating mode/ODR (CTRL_REG1, 0x20; CTRL_REG4, 0x23 for Z), and conversion mode (CTRL_REG3, 0x22). Turn-on time from wakeup command to data (AN4602 Table 8): 1.2 ms (LP) to 6.65 ms (UHP).
5. Each conversion sets ZYXDA in STATUS_REG (0x27) and raises DRDY (PMOD pin 2 via R4). Reading the output registers clears DRDY. The programmable threshold interrupt appears on INT (PMOD pin 1 via R3) when enabled via INT_CFG (0x30).

There is no power switch, regulator, or level shifter on the module; the PMOD 3V3 rail powers U1 directly, and #FLG01/#FLG02 in the schematic are ERC-only power-flag artifacts with no physical part.

4. Interfaces#

PMOD pin map (Type 6 extended, J1 = 2x06 right-angle header)#

Pins 9/10 repeat the bus for daisy-chaining; 11/12 repeat GND/3V3.

Jumpers#

Test points#

None are defined in the schematic. Probe at the J1 pins and, after layout, at component pads. Adding TPs for SDA, SCL, 3V3, and DRDY is a reasonable layout-stage improvement.

5. Component-by-component review#

Every reference designator in generate_design.py is covered.

Key U1 datasheet parameters (LIS3MDL, DocID024204 Rev 4)#

6. Datasheet summary and design interpretation#

Official references: LIS3MDL datasheet (ST) (Pololu-hosted copy, DocID024204 Rev 4), AN4602 application note, DocID027014 (Pololu-hosted copy), Yageo RC thick-film resistors, LIS3MDL product page. Check the latest revision before procurement.

7. Expected values before bench testing#

All values are targets derived from the schematic and the datasheets above; none has been measured on hardware.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin-1 dot) against the LGA-12 footprint; the package is 2 × 2 mm and unforgiving.
• Verify ~CS is tied to 3V3 (nets u1/cs), not left floating: floating ~CS can drop into SPI mode and hang the bus.
• Verify C1 is on the C1 pin (pin 4) net C1_REG, and C2/C3 are on 3V3. Swapping C1 and C2 nets is the classic error on this part.
• Confirm JP3 default bridge is 1-2 (SA1 to GND, address 0x1C) and matches the README/host software.
• Confirm JP1/JP2 are bridged for a single-module bench.
• Check R3/R4 orient sensor → host only (they carry sensor-driven signals to PMOD pins 1/2; PMOD host must configure those pins as inputs).
• Check PMOD pin numbering against the Digilent spec: top row 1–6, bottom row 7–12, with the zigzag mapping the library applies to the 2x06 header.
• Confirm no part is fitted for #FLG01/#FLG02 (schematic artifacts only).
• After layout (future): sensor away from the header current loop, >10 mA traces a few millimeters from U1, C1/C2 close to U1.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record everything against board serial, equipment, and date (Section 11). PMOD host at 3.3 V or a current-limited 3.3 V bench supply wired to J1 pins 6/12 (3V3) and 5/11 (GND).

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND in both polarities; investigate any hard short.
3. Pull-up jumper verification (fitted default): measure SDA (J1 pin 4) to 3V3 (pin 6): expect ≈4.7 kΩ. Measure SCL (pin 3) to 3V3: ≈4.7 kΩ.
4. If this module will join a chain that already has pull-ups, cut JP1/JP2 and re-measure: both readings must go open (only leakage). Re-verify the remaining chain still shows one 4.7 kΩ pull-up per line.
5. Verify JP3 center (ADDR) reads ≈0 Ω to GND (default) or ≈0 Ω to 3V3 if deliberately restrapped — never both.

B. First power, idle current, bus idle levels#

1. Apply 3.3 V with a 50 mA limit. Expect a brief charging blip, then microamp-range idle current (device boots to power-down in ~3.2 ms).
2. Probe SDA and SCL: both must sit at 3.3 V through the pull-ups with the bus idle. A line stuck low means a solder bridge, damaged U1, or a host pin driving low.
3. Probe MAG_INT and MAG_DRDY: defined CMOS levels, DRDY low after startup.

C. Address-ACK scan#

1. Run an I2C scan at 100 kHz. Expect an ACK at exactly 0x1C (7-bit) with JP3 in 1-2, and nothing else from this module.
2. If JP3 is restrapped 2-3, rescan: ACK at 0x1E only.
3. Ghost ACKs at both addresses suggest a floating SA1 (bad JP3 joint).

D. First transaction: WHO_AM_I#

1. Write: START, 0x38 (SAD+W for 0x1C), SUB 0x0F; repeated START, 0x39 (SAD+R), read 1 byte, NACK, STOP.
2. Expected response byte: 0x3D. (With JP3 2-3 the bytes are 0x3C/0x3D for SAD+W/R.)
3. Read CTRL_REG1 (0x20) and CTRL_REG3 (0x22): expect the reset defaults 0x10 and 0x03.

E. Built-in self-test (AN4602 Section 5, Figure 6)#

Keep the module still and away from magnets for the whole test.

1. Initialize: write 0x1C → CTRL_REG1 (0x20) (ODR 80 Hz), 0x40 → CTRL_REG2 (0x21) (FS ±12 gauss), 0x00 → CTRL_REG3 (0x22) (continuous). Wait 20 ms.
2. Wait for ZYXDA in STATUS_REG (0x27), read OUT_X/Y/Z (0x28–0x2D, multi-byte read with SUB MSB set: SUB = 0xA8) and discard the first sample. Then collect 5 samples and average per axis → OUT_NOST.
3. Enable self-test: write 0x1D → CTRL_REG1 (ST bit set). Wait 60 ms.
4. Again discard the first sample, average 5 samples → OUT_ST.
5. Pass bands (datasheet Table 3 / AN4602 Table 17, FS ±12 G, absolute values, sensitivity 2281 LSB/gauss):

• X: 1.0 G ≤ |ST−NOST| ≤ 3.0 G (2281–6843 LSB)
• Y: 1.0 G ≤ |ST−NOST| ≤ 3.0 G (2281–6843 LSB)
• Z: 0.1 G ≤ |ST−NOST| ≤ 1.0 G (228–2281 LSB)

1. Disable: write 0x1C → CTRL_REG1, then 0x03 → CTRL_REG3 (power-down).

F. Field sanity checks#

1. Configure FS ±4 G, UHP, 20 Hz continuous (AN4602 wakeup: 0x40 → 0x21 for FS ±12 is the app-note default; for this check use FS ±4, CTRL_REG2 = 0x00). Compute magnitude sqrt(X²+Y²+Z²) scaled by 6842 LSB/gauss.
2. With the module still and away from steel/magnets, expect a stable magnitude of roughly 0.25–0.65 gauss (Earth's field; value depends on location). A magnitude near zero or near full scale indicates a stuck axis, wrong scaling, or magnetized surroundings.
3. Rotate the module slowly through 360°: X/Y should trace approximately a circle (before calibration, an offset circle); heading atan2(Y, X) should sweep monotonically.
4. Bring a small magnet within a few centimeters briefly: readings must respond strongly and, close in, MROI (INT_SRC overflow bit) may set. Remove it and confirm readings return to the Earth-field baseline (an offset shift after this test means the 50 gauss disturbance limit was exceeded — keep the magnet farther away).

G. DRDY and interrupt path#

1. In continuous mode, scope MAG_DRDY (PMOD 2): expect toggling at the ODR; confirm it clears when the output registers are read.
2. Program INT_THS (0x32/0x33) below the ambient field, enable XIEN/IEN in INT_CFG (0x30), and confirm MAG_INT (PMOD 1) asserts and INT_SRC (0x31) reports the axis; with LIR latched, confirm reading INT_SRC releases it.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic follows the LIS3MDL datasheet connection scheme closely: the internal-regulator capacitor is present on the C1 pin, both supplies are decoupled, ~CS locks I2C mode, and SA1 is strapped by JP3 rather than left floating. The chaining scheme (bus repeated on pins 9/10, pull-ups behind JP1/JP2) is coherent, provided exactly one module per chain keeps its jumpers bridged. The principal open risks are the unbuilt PCB (layout must keep current loops away from the sensor and get the LGA-12 footprint right), the unverified interaction of 100 Ω series resistors with the host's input thresholds, and the fact that every number above — including the self-test pass bands and Earth-field expectation — is a datasheet target that no physical board has yet met.