Sensor modules

AXS-050 — OV7670 camera carrier dual-PMOD module (flagship)

Catalog #50 in the AruviX sensor line, level L5 (parallel DVP capture + SCCB configuration).

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CAM_D0 CAM_D1 CAM_D2 CAM_D3 CAM_D4 CAM_D5 CAM_D6 CAM_D7 CAM_HREF CAM_PCLK CAM_VSYNC D0 D1 D2 D3 D4 D5 D6 D7 GND HREF PCLK PWDN RESET_N SIOC SIOD VSYNC XCLK

Production status#

Source: boards/sensor-modules/axs-050-camera

Catalog #50 in the AruviX sensor line (../README.md), level L5 (parallel DVP capture + SCCB configuration).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Live video into the FPGA — the capstone of the sensor line. Generate a 24 MHz XCLK from a fabric PLL, configure the sensor over SCCB, then capture the parallel DVP stream: sample D0–D7 on PCLK edges while HREF is high, framed by VSYNC, into a line buffer / framebuffer. Clock-domain crossing, BRAM streaming, and timing constraints all show up here for real.

Dual-PMOD requirement#

This module has two PMOD plugs and needs two adjacent sockets on the ECP5 host (matching the host board's paired-PMOD spacing):

• J1 (PMOD A) — 8-bit pixel data D0–D7.
• J3 (PMOD B) — PCLK, XCLK, HREF, VSYNC, SCCB (SIOC/SIOD), RESET_N, PWDN.

Camera socket (J2)#

A stock 2×9 pin socket (Connector_PinSocket_2.54mm:PinSocket_2x09_P2.54mm_Vertical) for the common 18-pin no-FIFO OV7670 breakout. The KiCad odd/even numbering matches the common breakout's own numbering:

Order-check warning: 18-pin OV7670 breakouts are mostly-but-not-always identical. Verify your board's silkscreen against this table before fitting.

Design#

• All camera-driven lines pass 100 Ω series: D0–D7 (R1–R8), PCLK (R9), HREF (R10), VSYNC (R11). XCLK is host-driven, wired directly.
• SCCB is I2C-compatible (7-bit address 0x21, 100 kHz): SIOC/SIOD get fixed 4.7 k pull-ups (no solder jumpers — the bus is dedicated to this camera, never chained).
• RESET_N: 10 k pull-up (camera runs by default); PWDN: 10 k pull-down (camera powered by default). Both host-controllable on J3 pins 9/10.
• 100 nF + 10 µF at the camera socket.
• XCLK = 24 MHz from a fabric PLL; PCLK returns at up to 24 MHz — treat it as a real clock (dedicated input routing, its own clock domain).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout: plug spacing must match the ECP5 host's adjacent PMOD sockets exactly; length-match the D bus loosely; PCLK away from XCLK
• [ ] Verify OV7670 breakout pinout against a purchased board
• [ ] hdl/: SCCB master, capture front-end (PCLK domain), line buffer + CDC FIFO, test-pattern check, testbench, ECP5 demo
• [ ] BOM export and availability check, design-review checklist