Actuator modules

AXA-003 — Motor encoder interface PMOD module

Catalog #3 in the AruviX actuator line, level L2. Six conditioned digital inputs — two quadrature pairs for N20/JGA25-class gearmotor encoders plus two spare hall/limit inputs — through a 74HC14 hex Schmitt inverter.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 E1A E1A_F E1A_INV E1A_RAW E1B E1B_F E1B_INV E1B_RAW E2A E2A_F E2A_INV E2A_RAW E2B E2B_F E2B_INV E2B_RAW GND H1 H1_F H1_INV H1_RAW H2 H2_F H2_INV H2_RAW

Production status#

Source: boards/actuator-modules/axa-003-encoder

Catalog #3 in the AruviX actuator line (../README.md), level L2. Six conditioned digital inputs — two quadrature pairs for N20/JGA25-class gearmotor encoders plus two spare hall/limit inputs — through a 74HC14 hex Schmitt inverter.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Hardware quadrature decode at MHz edge rates — the signature FPGA-beats-MCU demo. A software loop polls; fabric counts every edge of both phases with a glitch filter, at any speed the motor can produce. Pairs with AXA-001 (dual DC driver) for the closed-loop PID lab.

Design#

• 74HC14D,653 (Nexperia), SOIC-14. One gate per channel, powered from 3V3, 100 nF decoupling.
• Per channel: 10 kΩ pull-up to 3V3 (encoder outputs are often open-collector), 1 kΩ + 10 nF RC filter (fc ≈ 16 kHz, strips motor-wire noise), Schmitt input squares the slow RC edge, inverter output → 100 Ω series resistor → PMOD (all six lines are module-driven).
• Every channel is INVERTED by the Schmitt stage. Quadrature decoding doesn't care (A/B inversion preserves the code sequence), but level-sensitive uses of H1/H2 (hall, limit switches) must invert in fabric.
• J2/J3: 1x04 pin sockets, pin order 3V3 / GND / A / B — verify your encoder breakout's wire order before plugging (breakouts vary; swapping 3V3/GND kills the hall sensors).
• J4: 1x03 pin header for the spare inputs (H1 / H2 / GND).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (20 × 40 mm actuator outline), DRC, fab outputs
• [ ] hdl/: quad_decoder (4×-count with glitch filter), testbench, demo
• [ ] BOM export and availability check, design-review checklist