I/O modules

AXO-011 — MAX98357A I2S class-D amplifier PMOD module

Catalog #11 in the AruviX output line, level L4 (I2S). Completes the audio path the I2S mics (axs-028/029) started: record → filter in fabric → play back. A MAX98357A PCM-input class-D mono amplifier drives a speaker terminal directly — no analog signal chain to build.

Level L4 ERC clean DRC clean Fab package 8 components

3D render of the AXO-011 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	VDD decoupling at U1	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	VDD bulk for class-D switching/audio peaks	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	SPEAKER 4-8R	Speaker output: 1 OUT+ 2 OUT- (bridge-tied load - do NOT ground either terminal)	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal`
`JP1`	SD_MODE	1-2 (default): SD_MODE via R1 to 3V3 = (L+R)/2 mono; 2-3: GND = shutdown	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`JP2`	GAIN 12/9/6dB	Open (default): GAIN floats = 9 dB; bridge 1-2 GND = 12 dB; bridge 2-3 3V3 = 6 dB	—	`SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm`
`R1`	1M	SD_MODE select: 1M vs internal 100k pull-down = 0.30 V = (L+R)/2; 220k = RIGHT, 100k = LEFT	`RC0603FR-071ML` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	MAX98357A	PCM-input class-D mono amplifier, I2S, 3.2 W at 5 V / ~1.4 W at 3.3 V into 4R	`MAX98357AETE+T` Analog Devices (Maxim) Datasheet ↗	`TQFN-16-1EP_3x3mm_P0.5mm_EP1.23x1.23mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 BCLK DIN GAIN GND LRCLK SD_MODE SD_SEL SPK_N SPK_P

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/io-modules/axo-011-i2s-amp

Catalog #11 in the AruviX output line (../README.md), level L4 (I2S). Completes the audio path the I2S mics (axs-028/029) started: record → filter in fabric → play back. A MAX98357A PCM-input class-D mono amplifier drives a speaker terminal directly — no analog signal chain to build.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

The transmit side of I2S (i2s_tx core): LRCLK/BCLK generation, 16/32-bit frames, and closing the record→DSP→playback loop against axs-028. The amp auto-detects the BCLK/LRCLK ratio (8–96 kHz sample rates, BCLK ≤ 12.288 MHz).

Design#

MAX98357AETE+T, TQFN-16 (stock symbol Audio:MAX98357A, stock footprint Package_DFN_QFN:TQFN-16-1EP_3x3mm_P0.5mm_EP1.23x1.23mm — verified).
PMOD Type 7 exactly per ../../pmod-common/PMOD-SPEC-NOTES.md: the host drives the DAC-data slot on pin 2; the ADC slot (pin 3) is NC.
Runs from PMOD 3V3 — no external rail. A bridged class-D gives ~1.4 W into 4 Ω at 3.3 V (the ~3.2 W headline needs 5 V, per the datasheet output power curves) — plenty for the lesson. Sustained full-scale sine into 4 Ω would exceed the ~100 mA PMOD guidance; music/speech duty cycles are fine.
SD_MODE strap (JP1 + R1): the pin has an internal 100 kΩ pull-down and selects mode by voltage: <0.16 V shutdown, 0.16–0.77 V (L+R)/2, 0.77–1.4 V right, >1.4 V left. Default JP1 1-2 routes SD_MODE through R1 = 1 MΩ to 3V3 → 0.30 V = (L+R)/2 mono (send a normal stereo frame, the amp mixes). JP1 2-3 = GND = hard shutdown. Fit R1 = 220 k for RIGHT (1.03 V) or 100 k for LEFT (1.65 V).
GAIN strap (JP2, open 3-way): datasheet table — 100 k→GND 15 dB, GND 12 dB, open 9 dB (default), VDD 6 dB, 100 k→VDD 3 dB. Bridge 1-2 for 12 dB, 2-3 for 6 dB; the 15/3 dB corners need a hand-fitted 100 k.
Speaker: J2 screw terminal, bridge-tied load — never ground either terminal, never share speaker returns.
100 nF + 10 µF on VDD (datasheet pair). Exposed pad to GND.
Library note: the stock symbol types the exposed pad unspecified, which trips a pin-type ERC warning against power-input GND; the generator retypes that one pin passive in the embedded copy (electrically true — it is a passive ground/thermal connection). Geometry is untouched.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	LRCLK	DIN (host out)	NC	BCLK	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (short/wide speaker traces, EP thermal vias), DRC, fab outputs
[ ] hdl/: i2s_tx core + WAV/sine playback demo, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist