Comms modules

AXC-004 — RFM95W LoRa radio PMOD module

Catalog #4 in the AruviX comms line, level L3 (SPI + DIO IRQs). HopeRF RFM95W (Semtech SX1276) for 915 MHz LoRa links; fit the RFM95W-868S2 variant for the EU band (same footprint).

Level L3 ERC clean DRC clean Fab package 11 components

3D render of the AXC-004 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Module HF decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	TX burst bulk (PA draws ~120 mA at +20 dBm)	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	u.FL	u.FL RF receptacle for a 915 MHz whip/patch antenna	`U.FL-R-SMT-1(10)` Hirose Datasheet ↗	`U.FL_Hirose_U.FL-R-SMT-1_Vertical`
`J3`	ANT WIRE PAD	Quarter-wave wire antenna pad (~78 mm at 915 MHz)	`wire antenna solder pad` n/a	`SolderWire-0.127sqmm_1x01_D0.48mm_OD1mm`
`JP1`	ANT: uFL/PAD	Antenna route: 1-2 (default) u.FL J2; 2-3 wire solder pad J3	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`R1`	100R	Series protection on the module-driven MISO line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection on the module-driven DIO0 (TX/RX done IRQ) line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Series protection on the module-driven DIO1 (RX timeout IRQ) line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	10k	~RST idle pull-up (SX1276 POR completes with the pin released)	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	RFM95W-915S2	LoRa transceiver module, SX1276, 915 MHz, SPI (footprint assigned: symbol has no default)	`RFM95W-915S2` HopeRF Datasheet ↗	`HOPERF_RFM9XW_SMD`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ANT ANT_PAD ANT_UFL CS_N DIO0 DIO1 GND LORA_DIO0 LORA_DIO1 LORA_MISO MISO MOSI RST_N SCK

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/comms-modules/axc-004-lora

Catalog #4 in the AruviX comms line (../README.md), level L3 (SPI + DIO IRQs). HopeRF RFM95W (Semtech SX1276) for 915 MHz LoRa links; fit the RFM95W-868S2 variant for the EU band (same footprint).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

SPI register control of a real radio, LoRa spreading-factor/bandwidth trade-offs, and interrupt-driven RX/TX state machines: DIO0 (TX-done / RX-done) and DIO1 (RX-timeout) both reach PMOD pins per the platform interrupt rule. Flagship project: months-on-a-charge field sensor with SCD40/BME280 + a battery board.

Design#

Footprint note (per line README): the stock RFM95W symbol ships with no default footprint — RF_Module:HOPERF_RFM9XW_SMD is assigned explicitly at capture.
PMOD Type 2A: 1 ~CS(NSS), 2 MOSI, 3 MISO via 100 Ω, 4 SCK, 7 DIO0 via 100 Ω, 8 ~RST with 10 k pull-up, 9 DIO1 via 100 Ω. SPI mode 0, ≤ 10 MHz.
DIO2–DIO5 left open (unused in the LoRa lessons).
Antenna: JP1 solder jumper — 1-2 (default) routes ANT to the u.FL receptacle (Hirose U.FL-R-SMT-1, stock footprint verified); 2-3 routes to a wire solder pad (J3) for a ~78 mm quarter-wave whip.
100 nF + 10 µF local decoupling (PA bursts ~120 mA at +20 dBm).
RF keep-out (line rule): no pour under the module's antenna pin or the 50 Ω feed; antenna edge faces away from the PMOD plug.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	~CS	MOSI	MISO	SCK	GND	3V3	DIO0	~RST	DIO1	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (50 Ω feed to J2/J3, RF keep-out, module castellations), DRC, fab outputs
[ ] Regulatory note: TX duty-cycle limits per band in the lesson text
[ ] hdl/: lora_phy driver core, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist