Lab modules

AXL-003 — Fast waveform generator PMOD module (8-bit R-2R DAC)

Catalog #3 in the AruviX lab line, level L4 (instrument). Pairs with AXL-002 as its own test source; DDS at MHz rates where the MCP4725 lab (axo-010) tops out at audio.

Level L4 ERC clean DRC clean Fab package 23 components
3D render of the AXL-003 PCB
Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

RefValueWhat it does on this boardPart numberFootprint
C1 100nF 16V X7R U1 op-amp decoupling GRM188R71C104KA01D
Murata
C_0603_1608Metric
C2 10uF 10V X5R U1 bulk decoupling (fast edges into capacitive loads) GRM21BR61A106KE19L
Murata
C_0805_2012Metric
J1 PMOD PLUG 2x6 PMOD peripheral plug (Digilent spec 1.2) not selected
generic
PinHeader_2x06_P2.54mm_Horizontal
J2 WAVE OUT Waveform output header: 1 signal, 2 GND (parallel with the BNC) not selected
generic
PinHeader_1x02_P2.54mm_Vertical
J3 BNC BNC output, parallel with J2 (stock footprint verified) B6252HB-NPP3G-50
Amphenol RF
Datasheet ↗
BNC_Amphenol_B6252HB-NPP3G-50_Horizontal
R1 2k 1% R-2R bit leg for D0 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R2 2k 1% R-2R bit leg for D1 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R3 2k 1% R-2R bit leg for D2 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R4 2k 1% R-2R bit leg for D3 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R5 2k 1% R-2R bit leg for D4 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R6 2k 1% R-2R bit leg for D5 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R7 2k 1% R-2R bit leg for D6 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R8 2k 1% R-2R bit leg for D7 (2R) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R9 1k 1% R-2R chain resistor LAD0 -> LAD1 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R10 1k 1% R-2R chain resistor LAD1 -> LAD2 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R11 1k 1% R-2R chain resistor LAD2 -> LAD3 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R12 1k 1% R-2R chain resistor LAD3 -> LAD4 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R13 1k 1% R-2R chain resistor LAD4 -> LAD5 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R14 1k 1% R-2R chain resistor LAD5 -> LAD6 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R15 1k 1% R-2R chain resistor LAD6 -> LAD7 (R) RC0603FR-071KL
Yageo
Datasheet ↗
R_0603_1608Metric
R16 2k 1% R-2R LSB terminator (2R to GND) RC0603FR-072KL
Yageo
Datasheet ↗
R_0603_1608Metric
R17 100R Series back-termination / short-circuit protection on the output RC0603FR-07100RL
Yageo
Datasheet ↗
R_0603_1608Metric
U1 OPA356 200 MHz CMOS rail-to-rail op-amp, unity buffer on the ladder output OPA356AIDR
Texas Instruments
Datasheet ↗
SOIC-8_3.9x4.9mm_P1.27mm

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 D0 D1 D2 D3 D4 D5 D6 D7 GND LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 WAVE_BUF WAVE_OUT

Production status#

Schematic ERC0 violations
PCB layoutcomplete
DRC0 violations
Fab packageexported (24 gerbers + drill + CPL + BOM)
Fabricatedno — design stage only

Source: boards/lab-modules/axl-003-wavegen


Catalog #3 in the AruviX lab line (../README.md), level L4 (instrument). Pairs with AXL-002 as its own test source; DDS at MHz rates where the MCP4725 lab (axo-010) tops out at audio.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

The dds_fast core: a phase accumulator + waveform table driving a parallel DAC every fabric clock. Update-rate math: at a 25 MHz sample clock, Nyquist allows <12.5 MHz, but with only ~2.5 samples per cycle and ladder/buffer settling, ~10 MHz is the usable ceiling — measure the roll-off and the images on AXL-002. Second lesson: R-2R accuracy vs resistor tolerance — with 1% parts the MSB leg error alone can reach ~2 LSB at 8 bits; measure INL/DNL and see why real DACs use trimmed networks.

Design#

PMOD pin123456789101112
NetD0D1D2D3GND3V3D4D5D6D7GND3V3

Regenerate#

python3 generate_design.py

Remaining for release#