Power boards

robot-power-dist — Robot power distribution board

Companion power board named (Phase B — robot power). A main-line board, not a PMOD module: it fans a battery rail out to four fused, current-monitored channels behind one soft-switch / e-stop master gate.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 EN GATE_STATUS GND LED1_A LED2_A LED3_A LED4_A LOOP_A LOOP_B PGATE PWR_ALERT_N SCL SCL_PU SDA SDA_PU ST_DIV VBAT VDIST VF1 VF2 VF3 VF4 VOUT1 VOUT2 VOUT3 VOUT4

Production status#

Source: boards/robot-power-dist

Companion power board named in ../actuator-modules/README.md (Phase B — robot power). A main-line board, not a PMOD module: it fans a battery rail out to four fused, current-monitored channels behind one soft-switch / e-stop master gate.

Status: schematic generated, ERC clean (0 errors / 0 warnings), netlist membership verified exactly (27 nets / 149 pins). PCB layout not started. Not released.

NOT A CERTIFIED SAFETY DEVICE. Safety-themed power gating only: no redundancy, no monitored contacts, no rated stop category. Never make a person's safety depend on it. Pairs with ../actuator-modules/axa-012-estop/ and the same fabric supervision contract.

Requirements#

• Input: VBAT 6.4–12.6 V (2S/3S LiPo) from battery-power-input/, which already provides the input fuse and reverse protection — this board deliberately does not duplicate them.
• One master ON/OFF authority in the power path: NC e-stop loop AND host enable, default OFF.
• Four independently fused output channels, each with high-side current and bus-voltage telemetry over I2C, one shared alert line.
• 3.3 V telemetry domain supplied by the host (Qwiic), fully separate from the battery power path.

Architecture#

VBAT (J1) ──► Q1‖Q2 (2x DMP4015SSS, high-side) ──► VDIST ─┬─► F1 ─ shunt ─► J3 CH1 (INA226 U1, 0x40)
                    ▲ PGATE                               ├─► F2 ─ shunt ─► J4 CH2 (INA226 U2, 0x41)
     R1 100k (OFF) ─┤ + D1 BZT52C10 clamp                 ├─► F3 ─ shunt ─► J5 CH3 (INA226 U3, 0x44)
   PGATE ► R2 10k ► J2 NC loop ► Q3 2N7002 ► GND          └─► F4 ─ shunt ─► J6 CH4 (INA226 U4, 0x45)
                        ▲ EN (J9.1, R3 10k pull-down)

Master gate (axa-012 topology, scaled up)#

Q1+Q2 are two DMP4015SSS (−40 V, −9.1 A rated, R_DS(on) 7 mΩ typ / 11 mΩ max at V_GS = −10 V, SO-8) in parallel, sources on VBAT, drains on VDIST, gates common on PGATE. The only pull-down path is the series chain PGATE → R2 (10k) → J2 e-stop loop (NC) → Q3 (2N7002) → GND, with R1 (100k) holding the gate at the source (OFF) and R3 (10k) holding EN low.

• Gate drive: R1/R2 form a 100k:10k divider, so V_SG = 0.909·VBAT — 5.8 V at 6.4 V (R_DS spec at −4.5 V still applies: ≤ 15 mΩ) and 11.5 V at 12.6 V, which D1 (BZT52C10) clamps to ≤ 10 V. The DMP4015SSS gate rating is ±20 V; the clamp is margin, not survival.
• Parallel R_DS(on) sharing caveat: the two FETs are not matched, so the static split is unequal; the positive R_DS tempco self-balances, but budget ~5 A per-FET comfort zone → ~8 A combined with margin (an even 4 A/4 A split dissipates ≈ 0.18 W per FET at the 11 mΩ max corner).
• No auto-relatch is a fabric contract, not a hardware feature. The AND is combinational: if the loop recloses while EN is still high, power returns. Host HDL must latch a GATE_STATUS drop and require a deliberate EN toggle — same contract as axa-012.
• J2 unused = fit a wire link; the board ships OFF until the loop is closed.

Distribution channels#

Each channel: VDIST → fuse (1206) → 20 mΩ shunt (2512) → screw terminal, with an INA226 across the shunt and a green output-live LED (4.7k, ≈ 2.2 mA at 12.6 V) on the output net.

• Metering full scale: INA226 shunt input range is ±81.92 mV (LSB 2.5 µV), so 81.92 mV / 20 mΩ = 4.096 A full scale per channel. Above that the reading saturates (no damage below the 36 V input limits).
• Shunt: 20 mΩ 1% 1 W 2512 (TBD-confirm: Vishay WSL2512R0200FEA18); dissipation at full scale is 0.34 W.

INA226 supply split (important)#

• VS pins (pin 6) run from the 3V3 telemetry rail — never from VDIST. The INA226 operating supply is 2.7–5.5 V (6 V absolute max); a 2S/3S battery rail would destroy it.
• The shunt/bus inputs (IN+/IN−/VBUS) are rated to 36 V common mode (datasheet: CM 0–36 V, V_VBUS abs max 40 V), so measuring the battery rail while powered from 3.3 V is exactly the intended use.
• Consequence: with the host unplugged the gate is OFF (EN pull-down) and the monitors are unpowered — telemetry only exists when the host does.

INA226 address map (datasheet SBOS547B, Table 6-2)#

(0x42/0x43 would need SDA/SCL straps; only GND/VS codes are used here.)

Telemetry and control interfaces#

• Shared 4.7k I2C pull-up pair (R12/R13) behind bridged solder jumpers JP1/JP2 — cut them when the host chain already provides pull-ups.
• All four INA226 ALERT outputs (open-drain) are wire-OR'd on PWR_ALERT_N with a single 10k pull-up (R14) to 3V3.
• GATE_STATUS math: VDIST through R15/R16 = 39k/10k, tap = VDIST·10/49 = 2.57 V at 12.6 V (1.31 V at 6.4 V), through R17 100R series. The tap can never exceed 3.3 V-safe levels below a 16 V rail. For 2S-only systems repopulate R15 = 18k (8.4 V → 3.0 V, 6.4 V → 2.29 V).

Fuse selection (ratings are load-specific)#

F1–F4 are 1206 SMD fuses, fitted 2 A by default (TBD: Littelfuse 0467002.NR). Suggested values:

Pick the fuse above the continuous load but sized so a stalled motor still opens it; remember the INA226 reading saturates at 4.1 A, so channels fused above 4 A lose metering headroom before the fuse acts. Total across the four channels must respect the ~8 A master-gate budget and the upstream battery-power-input/ fuse.

Part substitutions / deviations from the pinned spec#

• Fuse MPN: the spec named the Littelfuse 0466 NANO2 series, but the pinned stock footprint is Fuse:Fuse_1206_3216Metric and a NANO2 body (6.1 × 2.7 mm) does not fit a 1206 land. The BOM therefore suggests the Littelfuse 0467 series (1206 form); switch to 0466 at layout time only with its own land pattern.
• GATE_STATUS divider: spec said "100k/10k like axa-012, scaled for 12.6 V". 100k/10k yields only 1.15 V at 12.6 V (never logic-high), so the fitted top resistor is 39k — exactly axa-012's own documented repopulation value for 12 V-class rails; topology unchanged.
• Terminal blocks, headers, zener, fuse and shunt MPNs carry TBD: / TBD-confirm: prefixes until an orderable-stock check pins them.

Regenerate and verify#

python3 generate_design.py
/Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli sch erc \
  --severity-all --format report --output reports/erc.rpt robot-power-dist.kicad_sch
# must report: 0 Errors 0 Warnings

Then export the netlist (kicad-cli sch export netlist --format kicadsexpr) and check every net's membership against the architecture above — ERC alone does not catch off-pin labels.

Remaining for release#

• [ ] PCB layout (wide VBAT/VDIST copper, shunt Kelvin-ish routing into the INA226 inputs, channel terminals on one edge), DRC, fab outputs
• [ ] Pin the TBD: MPNs (fuses, shunt, zener, terminals) and export the BOM
• [ ] Consider VDIST bulk capacitance once real motor loads are chosen
• [ ] hdl/: power-supervisor FSM (GATE_STATUS latch, EN toggle relatch, PWR_ALERT_N handling) shared with axa-012
• [ ] Bench: gate truth table, per-channel calibration (shunt tolerance), fuse-blow sanity test, design-review checklist