Sensor modules

AXS-022 — Dual IR reflective sensor PMOD module

Catalog #22 in the AruviX sensor line, level L1 (GPIO). Two onsemi QRE1113GR reflective pairs (IR LED + phototransistor) for line-following and edge detection at ~3 mm range.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 GND IR1 IR1_LED IR1_SENSE IR2 IR2_LED IR2_SENSE

Production status#

Source: boards/sensor-modules/axs-022-ir-reflective

Catalog #22 in the AruviX sensor line (../README.md), level L1 (GPIO). Two onsemi QRE1113GR reflective pairs (IR LED + phototransistor) for line-following and edge detection at ~3 mm range.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Reflective optical sensing with two channels: detect a line, tell left from right, and see how surface albedo and distance change the analog collector swing behind the digital threshold.

Design#

• Each QRE1113GR: LED anode fed from 3V3 through 100 Ω (cathode to GND), phototransistor emitter to GND, collector loaded by 10 kΩ to 3V3. Reflection lights the transistor and pulls the collector low.
• LED current: the spec value 100 Ω gives ~(3.3 − 1.2)/100 ≈ 21 mA at the LED's nominal 1.2 V drop — inside the 50 mA rating with margin. 82 Ω (~26 mA) would buy a little more range; fit 82 Ω if your surfaces are dark, the pads are the same.
• Collector nodes pass 100 Ω series resistors to PMOD pins 1/2 (IR1, IR2).
• 100 nF decoupling for the switched LED currents.
• ERC note: generate_design.py relaxes exactly one KiCad pin-matrix cell (open emitter ↔ power output) in the project file, because the phototransistor emitters tie directly to the GND rail that also carries the mandatory PWR_FLAG. That is a valid common-emitter hookup; the default matrix is conservative. All other ERC checks stay at defaults.

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (20 × 25 mm outline, sensors on the board edge, face down)
• [ ] hdl/: dual-channel sampler + line-follow demo, testbench
• [ ] BOM export and availability check, design-review checklist