Power boards

battery-power-input — AruviX robot battery power board

Main-line board (not a PMOD module). This is the robot-power foundation named (Phase B): a 2S/3S hobby LiPo comes in, gets fused, reverse-protected, clamped, and metered, then feeds a raw motor rail plus independent 5 V and 3.3 V buck rails. All battery telemetry leaves the board on I2C (Qwiic + pin header).

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3_OUT 5V_OUT BATT_P BST_3V3 BST_5V EN3_3S EN5_3S EN_3V3 EN_5V GND I2C_ALERT LED3_A LED5_A Q1_GATE SCL SCL_PU SDA SDA_PU SW_3V3 SW_5V VBAT_FUSED VBAT_OUT VBAT_P

Production status#

Source: boards/battery-power-input

Main-line board (not a PMOD module). This is the robot-power foundation named in ../actuator-modules/README.md (Phase B): a 2S/3S hobby LiPo comes in, gets fused, reverse-protected, clamped, and metered, then feeds a raw motor rail plus independent 5 V and 3.3 V buck rails. All battery telemetry leaves the board on I2C (Qwiic + pin header).

Status: schematic capture complete — ERC 0 errors / 0 warnings (--severity-all), netlist-membership verified (23 nets / 123 pin memberships exact). PCB layout not started.

Regenerate and verify:

python3 generate_design.py
/Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli sch erc \
  --severity-all --format report --output reports/erc.rpt battery-power-input.kicad_sch

Requirements#

• Input: 2S/3S hobby LiPo, 6.4–12.6 V, up to the 5 A fuse rating.
• Protection: fuse, reverse polarity, surge clamp. Not cell-level protection (see safety boundary).
• Telemetry: bus voltage + current of the entire downstream load on I2C, with a programmable alert line.
• Outputs: raw metered battery rail (motor rails / robot-power-dist), 5 V / 2 A, 3.3 V / 2 A, each on its own screw terminal with GND.
• Input-UVLO on the logic rails, selectable for 2S or 3S floor.

Architecture (power chain)#

J1 (screw terminal) -> F1 5A 5x20 fuse -> Q1 DMP4015SSS ideal-diode P-FET -> VBAT_P
VBAT_P: D1 SMBJ16A TVS, 2x22uF + 100nF bulk, UVLO dividers
VBAT_P -> R1 10 mOhm shunt (INA226) -> VBAT_OUT
VBAT_OUT -> J2 raw motor rail
VBAT_OUT -> U2 AP63205WU -> 5V_OUT (J3)
VBAT_OUT -> U3 AP63203WU -> 3V3_OUT (J4)

Input connector#

Phoenix MKDS 3/2-5,08 screw terminal (stock KiCad footprint TerminalBlock_Phoenix_MKDS-3-2-5.08). XT60 has no stock footprint; use an XT60 pigtail into the terminal, or add a custom XT60 footprint in a later rev (open decision).

Reverse-polarity ideal diode — documented deviation#

The task spec pinned "source toward battery". That orientation does not block: with the battery reversed, the P-FET body diode (anode = drain, cathode = source) would be forward-biased from the load node into the reversed pack. Implemented the electrically correct orientation instead:

• Drain to battery (VBAT_FUSED), source to load (VBAT_P), gate to GND via R2 100k.
• Correct polarity: body diode (D→S) conducts first, then V_GS = −V_BAT enhances the channel (DMP4015SSS V_GS(th) max −1 V, R_DS(on) spec at −4.5 V/−10 V — fully enhanced at 6.4 V minimum pack voltage).
• Reversed: body diode is reverse-biased and V_GS ≥ 0 keeps the channel off.
• D2 BZT52H-C10 clamps V_SG to 10 V for 3S packs (V_GS abs max ±20 V; the clamp adds margin, ~26 µA through R2 at 12.6 V). Same Q1 + clamp + 100k part set as ../usb-c-pd-trigger/ (datasheet-verified there), different orientation for the ideal-diode role.

Surge clamp and bulk#

• D1 SMBJ16A unidirectional TVS (Device:D_TVS symbol per project convention; the schematic notes pin 1 = cathode = VBAT_P for layout). 16 V standoff clears the 12.6 V full-charge 3S voltage; breakdown 17.8–19.7 V.
• C1/C2 2×22 µF 25 V X7R 1210 (MPN TBD-confirm: Murata GRM32ER71E226KE15L) plus C3 100 nF.

Telemetry — INA226 high-side on the main feed#

Everything downstream of the protection (motor rail and both bucks) flows through the shunt, so the INA226 meters the whole robot.

• Shunt R1: 10 mΩ 1 % 3 W 2512 (MPN TBD-confirm: Vishay WSLP2512R0100FEA — verified 10 mΩ/3 W/2512. Note: the Bourns CSS2H-2512R-L100F suggested in the task pin is a 0.1 mΩ part, not 10 mΩ; do not substitute it).
• Range math: INA226 full-scale shunt input ±81.92 mV (TI SBOS547B §5/§7); 81.92 mV / 10 mΩ = 8.19 A range, current LSB 8.19 A/2^15 ≈ 0.25 mA. At the 5 A fuse rating the shunt drops 50 mV and dissipates I²R = 25 × 0.01 = 0.25 W in a 3 W part.
• IN+ to the supply side, IN− and VBUS to the load side (VBAT_OUT), per the datasheet pin table. VS = 3V3_OUT (2.7–5.5 V rated), 100 nF bypass.
• A0 = A1 = GND → I2C address 0x40.
• ALERT (open-drain) → R3 10k pull-up to 3V3_OUT → net I2C_ALERT → J6.
• I2C out on both J5 Qwiic JST-SH (stock SM04B-SRSS-TB footprint, pin order 1 GND, 2 3V3, 3 SDA, 4 SCL — SparkFun Qwiic standard) and J6 pin header. Deviation: J6 is 1x05, not the pinned 1x04, so the ALERT line has a pin (GND/3V3/SDA/SCL/ALERT); Qwiic cannot carry ALERT.
• R4/R5 4.7k bus pull-ups to 3V3_OUT behind the standard bridged solder jumpers JP1 (SDA) / JP2 (SCL), nets SDA_PU/SCL_PU — cut when the host bus already has pull-ups.

Bucks — AP63205WU (5 V) and AP63203WU (3.3 V), fed from VBAT_OUT#

Two independent Diodes TSOT-23-6 synchronous bucks, 2 A each, fed from the post-INA226 net so their current is metered. Values from the Diodes AP63200/01/03/05 datasheet DS41326 Rev. 3-2 (fetched 2026-07-14):

Deviations, with reasons:

• The task pin estimated L ≈ 6.8–10 µH; the datasheet's own tables for these 1.1 MHz fixed parts say 4.7 µH (5 V) and 3.9 µH (3.3 V) (6.8–10 µH is the 500 kHz AP63200/01 row). Datasheet values used.
• 3.9 µH has no stock Coilcraft XAL7030 footprint; nearest stock value 3.3 µH keeps ΔI_L at 34 % of 2 A, inside the datasheet's 30–50 % window.
• No power-good pin exists on the WU (TSOT-23-6) parts — verified against the pin table (FB/EN/VIN/GND/SW/BST only) — so each rail gets a green LED (D3 5V_OUT via R12 1k ≈ 3 mA; D4 3V3_OUT via R13 470R ≈ 2.5 mA).

Input-UVLO via the EN dividers#

Each buck has its own divider from VBAT_P to EN (EN abs max 35 V, so a direct divider is fine). Design per DS41326 §3 "Enable", Figure 22 and Eq. 1/Eq. 2: EN threshold 1.18 V rising / 1.10 V falling (the task pin said 1.14 V — the datasheet EC table says otherwise; datasheet used), EN pull-up current 1.5 µA disabled → 5.5 µA enabled.

Model (equivalent to Eq. 1/Eq. 2): V_ON = (1.18/(Rtop∥Rbot) − 1.5 µA)·Rtop, V_OFF = (1.10/(Rtop∥Rbot) − 5.5 µA)·Rtop.

Check against Eq. 1: R5 = (0.932·5.96 − 5.36)/4.1 µA = 47.5k ≈ 46.4k ✓; Eq. 2: R6 = 1.1·46.4k/(5.36 − 1.1 + 5.5 µA·46.4k) = 11.3k ✓.

Notes:

• The dividers hang off VBAT_P (pre-shunt), so their ~21 µA each is unmetered — negligible against the 0.25 mA current LSB.
• VBAT_OUT (motor rail) stays live below UVLO. Only the 5 V/3.3 V rails shut down; the FPGA fabric owns any motor-rail low-voltage policy.
• Set JP3/JP4 before first power-up with a 3S pack, else the logic rails run a 2S floor (harmless to the electronics, bad for the pack).

Fuse#

F1 5×20 fast fuse in clip holder, stock footprint Fuse:Fuseholder_Clip-5x20mm_Keystone_3517_Inline (2× Keystone 3517 clips per position). Fuse MPN TBD: Littelfuse 0217005.MXP (5 A fast) or equivalent. The fuse protects the wiring, not the loads.

Safety boundary — THIS BOARD IS NOT A BMS#

• No cell-level protection: no per-cell monitoring, balancing, over-charge, or over-discharge cutoff. Hobby packs with balance chargers are assumed.
• Low-voltage cutoff is a host/fabric responsibility using INA226 bus readings and the ALERT limit register. This board only implements the buck input-UVLO floors above, and the raw VBAT_OUT rail ignores even those.
• Reverse protection covers a miswired pack at J1; it does not protect against shorted outputs beyond F1.
• Prototype: bench validation (reverse input, short, thermal, UVLO trips, telemetry accuracy) required before the NOT-RELEASED line clears.

Datasheets used (application values, fetched 2026-07-14)#

• Diodes AP63200/AP63201/AP63203/AP63205, DS41326 Rev. 3-2 — <https://www.diodes.com/datasheet/download/AP63200-AP63201-AP63203-AP63205.pdf> (EN thresholds/currents, Eq. 1/2 UVLO, Tables 2/3 L/CIN/COUT/CBST, fixed-FB connection, no-PG pinout, EN abs max 35 V).
• TI INA226, SBOS547B — <https://www.ti.com/lit/ds/symlink/ina226.pdf> (±81.92 mV full scale, VS 2.7–5.5 V, VBUS 0–36 V, pinout, 0x40 addressing, open-drain ALERT, 100 nF bypass).
• Coilcraft XAL7030, Doc 863 — <https://www.coilcraft.com/getmedia/0d05a05e-d55d-4a0c-911d-46bd73686633/xal7030.pdf> (472: 4.7 µH/Isat 10.1 A/DCR 26 mΩ; 332: 3.3 µH/Isat 12.3 A/DCR 19.5 mΩ; MEC = tin-silver, 7-inch reel).
• Vishay WSLP2512R0100FEA (10 mΩ 1 % 3 W 2512) — distributor-verified (TME/Future/Vishay doc 30122).
• DMP4015SSS — <https://www.diodes.com/datasheet/download/DMP4015SSS.pdf> (same custom symbol block as ../usb-c-pd-trigger/, verified there).

Open decisions#

• XT60 input: no stock KiCad footprint. Rev 0.1 uses the MKDS 3 screw terminal + XT60 pigtail; a custom XT60-PW footprint is a candidate for the layout phase.
• Exact fuse MPN (5 A fast 5×20) and the TBD-confirm MPNs above (22 µF 1210, shunt) need distributor confirmation at order time.
• Whether robot-power-dist wants a second INA226 address (A0 strap) here or does its own per-channel metering (current plan: per-channel there).
• E-stop integration (actuator catalog #12) is scoped to robot-power-dist.

Release checklist#

• [x] ERC 0 errors / 0 warnings with --severity-all (reports/erc.rpt)
• [x] Netlist-membership check: 23 nets / 123 pin memberships exact
• [ ] PCB layout + DRC (high-current paths: J1→F1→Q1→R1→J2 sized for 5 A)
• [ ] Bench validation per safety-boundary section
• [ ] BOM export with confirmed MPNs