I/O modules

AXO-004 — MAX7219 8×8 LED matrix PMOD module

Catalog #4 in the AruviX output line, level L3 (SPI). The display-refresh job axo-002/axo-003 do in fabric, done by a dedicated controller: a MAX7219 scans an 8×8 matrix from 8 row registers written over SPI.

Level L3 ERC clean DRC clean Fab package 14 components

3D render of the AXO-004 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	MAX7219 supply decoupling (datasheet-required, close to V+)	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Bulk reservoir for matrix scan current (datasheet-required)	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`C3`	100nF 16V X7R	74AHCT125 supply decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J3`	EXT 5V IN	External 5 V for the MAX7219 and matrix: 1 +5V, 2 GND (common with PMOD GND)	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal`
`J4`	MATRIX PINS 1-8	8x8 matrix socket row: matrix pins 1-8 (1088AS-class common-cathode pinout)	not selected generic	`PinSocket_1x08_P2.54mm_Vertical`
`J5`	MATRIX PINS 9-16	8x8 matrix socket row: matrix pins 9-16 (1088AS-class common-cathode pinout)	not selected generic	`PinSocket_1x08_P2.54mm_Vertical`
`R1`	28k	Segment current set: RSET 28k -> ISEG ~20 mA at VLED 2.0 V (datasheet Table 11)	`RC0603FR-0728KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	MAX7219	Serially interfaced 8-digit/8x8 LED display driver, 5 V	`MAX7219CWG+` Analog Devices (Maxim) Datasheet ↗	`SOIC-24W_7.5x15.4mm_P1.27mm`
`U2`	74AHCT125	Quad 3-state buffer, TTL-threshold inputs (3.3 V -> 5 V level shift)	`SN74AHCT125D` Texas Instruments Datasheet ↗	`SOIC-14_3.9x8.7mm_P1.27mm`
`U2`	74AHCT125	Quad 3-state buffer, TTL-threshold inputs (3.3 V -> 5 V level shift)	`SN74AHCT125D` Texas Instruments Datasheet ↗	`SOIC-14_3.9x8.7mm_P1.27mm`
`U2`	74AHCT125	Quad 3-state buffer, TTL-threshold inputs (3.3 V -> 5 V level shift)	`SN74AHCT125D` Texas Instruments Datasheet ↗	`SOIC-14_3.9x8.7mm_P1.27mm`
`U2`	74AHCT125	Quad 3-state buffer, TTL-threshold inputs (unused gate parked)	`SN74AHCT125D` Texas Instruments Datasheet ↗	`SOIC-14_3.9x8.7mm_P1.27mm`
`U2`	74AHCT125	Quad 3-state buffer, TTL-threshold inputs (power unit)	`SN74AHCT125D` Texas Instruments Datasheet ↗	`SOIC-14_3.9x8.7mm_P1.27mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CLK_5V COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 CS_N DIN_5V EXT_5V GND ISET LOAD_5V MOSI ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 SCK

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/io-modules/axo-004-matrix

Catalog #4 in the AruviX output line (../README.md), level L3 (SPI). The display-refresh job axo-002/axo-003 do in fabric, done by a dedicated controller: a MAX7219 scans an 8×8 matrix from 8 row registers written over SPI.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

SPI to a real controller: 16-bit frames, register map (rows 0x1–0x8, decode/intensity/scan-limit/shutdown/display-test), LOAD-latched.
Level shifting done for a reason: the MAX7219 is a 5 V part — VIH is 3.5 V min at 5 V supply, so 3.3 V PMOD signals are not legal inputs. DIN/CLK/LOAD go through a 74AHCT125 (TTL 2.0 V thresholds in, 5 V out).

Design#

MAX7219CWG+ (SOIC-24W, stock footprint Package_SO:SOIC-24W_7.5x15.4mm_ P1.27mm verified), powered from the external 5 V screw terminal J3 (matrix can exceed 300 mA — never from the PMOD).
SN74AHCT125D (SOIC-14) as 3.3 V→5 V shifter; 3 gates used, gate 4 parked (input+enable grounded, output open). All enables grounded.
ISET: RSET = 28 kΩ V+→ISET per MAX7219 datasheet Table 11 → ISEG ≈ 20 mA at VLED = 2.0 V (red matrix class).
No MISO: the MAX7219 is write-only, so PMOD pin 3 is NC — a documented deviation from a full Type 2 port.
100 nF + 10 µF at the MAX7219 (datasheet-required pair), 100 nF at the 74AHCT125.

Matrix socket — orientation warning#

No stock 8×8 matrix footprint exists in KiCad 9 (verified against Display.pretty / Display_7Segment.pretty), so the matrix mounts in two 1×8 pin-socket rows: J4 = matrix pins 1–8, J5 = pins 9–16, wired for the common 1088AS-class common-cathode pinout (ROWn = DIG cathodes, COLn = SEG anodes). Matrix vendors are not consistent — check your part's datasheet and pin 1 before plugging. A common-anode 788BS works electrically transposed (swap rows/columns in HDL). Row spacing for the ~32 mm package is a layout-phase item.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	~CS (LOAD)	MOSI (DIN)	NC (no MISO)	SCK (CLK)	GND	3V3	NC	NC	NC	NC	GND	3V3

External power: J3 pin 1 = +5 V, pin 2 = GND (common with PMOD ground).

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (matrix row spacing per 1088AS package), DRC, fab outputs
[ ] hdl/: SPI master + MAX7219 init/frame driver, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist