← AXC-001

Circuit review & bench-test guide

AXC-001 — W5500 SPI Ethernet PMOD module

Document purpose#

This document explains the axc-001-ethernet-spi PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC report in reports/.

This board has never been fabricated. Repository status is schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started; not released. There is no PCB, no BOM export, no DRC record, and no first-article bench result. Every number below is a target to verify against real hardware, not a proven result. The analog front end is copied from the WIZnet W5500-Ref-RJ45WithMag reference schematic, which raises confidence in the topology but proves nothing about this layout-to-be or assembly.

1. What the board does#

The board puts a WIZnet W5500 — hardwired TCP/IP + MAC + PHY behind a plain SPI slave — on a PMOD Type 2A plug, with a Hanrun HR911105A integrated-magnetics RJ45. The FPGA host talks SPI (mode 0/3, up to 33 MHz sustained, 80 MHz burst per WIZnet) to 8 hardware sockets; ~INT signals socket events on PMOD pin 7. It is catalog #1 (L3) in the comms line and the "working web server in a weekend" half of the paired lesson with AXC-002 (LAN8720A soft MAC).

Functional block diagram#

PMOD host (3.3 V)          Module                                 Network
┌──────────────┐   ┌────────────────────────────────┐   ┌──────────────────┐
│ 1 ~CS ───────┼──>│ SCSn                           │   │                  │
│ 2 MOSI ──────┼──>│ MOSI        U1 W5500      TX± ─┼──>│ J2 HR911105A     │
│ 3 MISO <──R12┼───│ MISO   (TCP/IP+MAC+PHY)   RX± <┼───│ MagJack          │
│ 4 SCK ───────┼──>│ SCLK                           │   │ (magnetics +     │
│ 7 ~INT <──R13┼───│ INTn (o.d., R10 10k PU)        │   │  link/act LEDs   │
│ 8 ~RST ──────┼──>│ RSTn (R11 10k PU)              │   │  via R8/R9 330R) │
│ 6/12 3V3 ────┼─┬>│ VDD          Y1 25 MHz XI/XO   │   └──────────────────┘
│ 5/11 GND ────┼─┼─│ GND          C1/C2 18p, R7 1M  │
└──────────────┘ │ │ EXRES1: R6 12.4k 1%            │
          FB1 120R└>│ AVDD (3V3A)  TOCAP C7 4.7µ    │
                    │ termination: R1–R5, C3–C6     │
                    └────────────────────────────────┘

2. Safety and scope boundaries#

• Everything is 3.3 V; electrical hazard to people is negligible. The real risks are mis-assembly of the dense LQFP-48 and the analog termination bank, and time lost chasing "no link" symptoms that are actually cable, switch, or magnetics problems.
• Standalone bench work must use a current-limited 3.3 V supply (200 mA limit; the W5500 draws ~130 mA typical when the PHY is up).
• Ethernet is transformer-isolated at J2, so a live switch/router is safe to attach. Do not attach anything carrying PoE at 48 V until the Bob Smith / chassis-return arrangement (jack pin 8 to GND, chassis-split cap deferred to layout) has been reviewed for the deployment environment.
• The W5500 is not 5 V tolerant. Never drive SPI or ~RST from 5 V logic.
• ERC-clean is a schematic check only. No PCB exists; the MDI trace matching, 3V3A island, and jack placement are all unbuilt and unverified.
• A working ping is not EMC or safety certification, and the deferred 1 nF/2 kV chassis split means EMC behavior is explicitly open.

3. Power and control sequence#

1. 3V3 arrives from the PMOD host (pins 6/12) or the bench supply. FB1 (120 Ω @ 100 MHz) derives 3V3A for the analog bank; C9–C13 (100 nF) and C14/C15 (10 µF) decouple both rails.
2. The internal 1.2 V core regulator starts (C7 4.7 µF on TOCAP, C8 10 nF on 1V2OUT — both datasheet-mandated values).
3. Y1 (25 MHz, CL = 12 pF) oscillates across XI/XO with C1/C2 18 pF load caps and R7 1 MΩ feedback. No crystal, no chip: SPI reads will fail or return garbage.
4. R11 holds ~RST high so an unconfigured host cannot hold the part in reset; the host may still pulse ~RST low (≥500 µs recommended) for a clean start.
5. PMODE straps are left open; internal pull-ups latch PMODE=111 (all-capable auto-negotiation) at reset, exactly as the WIZnet reference does.
6. The PHY auto-negotiates with the link partner. LINKLED sinks through J2's green LED (anode fed from 3V3 via R8 330 Ω); ACTLED blinks the yellow LED via R9 on traffic.
7. The host reads VERSIONR (offset 0x0039, common register block) — the value is fixed at 0x04 — as the canonical "SPI path alive" check, then configures MAC/IP/socket registers. ~INT (open-drain, R10 10 k pull-up, R13 100 Ω series) falls on enabled socket/IP events.

4. Interfaces#

PMOD pin map (host viewpoint):

SPI: mode 0 or 3, W5500 frame = 16-bit address + control byte (block select, R/W, operation mode) + data. There are no test points defined yet (no layout exists); bench probing is at J1/J2 pins, the passives, and the LQFP pins under magnification.

5. Component-by-component review#

The board is dense (~30 nets), so components are grouped by function.

5.1 Controller, jack, and clock#

5.2 MDI termination and analog bias (WIZnet reference values)#

5.3 Host lines, LEDs, and decoupling#

Every ref-des on the board is covered above: U1, J1, J2, Y1, FB1, R1–R13, C1–C15.

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Verify U1 orientation (pin 1 dot) and inspect all four LQFP-48 sides for bridges/opens under magnification; 0.5 mm pitch.
• Confirm RSVD pins 23, 38–42 land on GND and VBG is truly floating on the final layout — buzz them.
• Measure R6 = 12.4 kΩ and confirm R1/R2/R4/R5 are 49.9 Ω 1 % before power.
• Confirm TX pull-ups go to 3V3A (not 3V3) and the RX terminations go to GND — the two banks look identical on a crowded board.
• Buzz U1 TXP/TXN/RXP/RXN to J2 TD+/TD−/RD+/RD− respectively; a pair swap here is the highest-value single check on the board.
• Verify J2 LED wiring: 3V3 → R8 → pin 9, pin 10 → LINKLED; 3V3 → R9 → pin 12, pin 11 → ACTLED. Verify pin 8 and SH to GND.
• Confirm Y1's GND pads (2/4) are soldered, C1/C2 are the 18 pF C0G parts, and the fitted crystal really is CL = 12 pF (MPN was TBD at capture).
• Confirm FB1 is fitted (an open bead is invisible to a digital-only test).
• At layout review (future): MDI pairs matched and short, termination bank tight to U1, 3V3A island under the analog side, jack off the far edge, >25 mil PMOD-clip clearance, and decide the 1 nF/2 kV chassis split.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment IDs, link-partner identity (switch model/port config), and cable type.

A. Unpowered inspection and resistance tests#

1. Visual inspection under magnification: U1 all sides, Y1 pads, the termination bank, J2 solder.
2. DMM: 3V3-to-GND and 3V3A-to-GND high resistance both polarities; 3V3-to-3V3A ≈ 0 Ω (FB1); R6 pad to GND = 12.4 kΩ; J1 pin 3 to U1 MISO ≈ 100 Ω; J1 pin 7 to 3V3 ≈ 10 kΩ (R10, through R13 in path: ~10.1 k).
3. Buzz all four MDI lines U1↔J2 and the LED network.

B. Standalone power-on (bench supply, no host, no cable)#

1. Feed current-limited 3.3 V (200 mA) into J1 pins 6/5. Record current: expect tens of mA rising toward ~130 mA class as the PHY runs.
2. Scope Y1: 25 MHz present and stable within ~10 ms of power.
3. Check ~RST high (R11), ~INT high (R10), both LEDs off (no cable).
4. No heating anywhere. A hot U1 with low current elsewhere suggests a rotated part — power off immediately.

C. Standalone SPI bring-up (bench SPI master: FT232H/Bus Pirate class)#

1. Connect a 3.3 V SPI master to J1 (~CS/MOSI/MISO/SCK, GND common). Start at ≤1 MHz SCK.
2. Read VERSIONR (block 0, offset 0x0039): must return 0x04. Repeat 100×; any miss is a wiring/solder/clock problem. Then re-run at the target SCK rate. This is the canonical bring-up gate — do not proceed until it is bulletproof.
3. Write/read-back a scratch register (e.g. GAR/SHAR) to prove MOSI as well as MISO.
4. Attach a cable to a live 100BASE-TX switch. Poll PHYCFGR (0x002E): LNK should assert within ~2 s; record negotiated SPD/DPX. Green LED must track LNK; unplug/replug and watch both.
5. Autonegotiation matrix: against a managed switch (or forced NIC), force the partner to 10/half, 10/full, 100/half, 100/full and confirm PHYCFGR reports the matching result each time. PMODE=111 means the W5500 advertises everything; a failure here points at the MDI analog path, not the straps.
6. Configure SHAR/GAR/SUBR/SIPR, open a UDP socket, and exchange packets with a PC. Confirm the yellow LED blinks with traffic and ~INT falls on RECV events when Sn_IMR is enabled (scope J1 pin 7).

D. Hosted bring-up (FPGA PMOD host)#

1. Plug into the ECP5 host. Confirm the host 3.3 V rail carries the ~130 mA load (this is at the edge of the ~100 mA PMOD guidance — record the rail voltage under load).
2. Run the spi_w5500 driver core: repeat the VERSIONR gate through fabric, first at low SCK, then at the target rate (≤33 MHz sustained).
3. Repeat the socket/ping exercise from C.6 through fabric/AruviOS; verify interrupt-driven RX (not polled) using ~INT on pin 7.
4. Soak: ping flood for 30 minutes; record error counters, current, and U1 temperature.

E. Robustness checks#

1. Cable matrix: short patch, long (≥30 m) cable, crossover, and both auto-MDIX orientations.
2. Power-cycle loop: 50 cold starts; VERSIONR gate + link-up each time.
3. Hot-plug the Ethernet cable repeatedly during traffic; confirm the stack recovers and ~INT storms don't wedge the driver.

F. Release-only tests#

EMC (radiated/conducted), ESD to the jack, the chassis-split decision (1 nF/2 kV vs direct GND at pin 8), and interop against a wider switch population are controlled-lab work, out of bench scope.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design leans deliberately on the WIZnet reference schematic — the termination values, crystal loading, EXRES1, TOCAP/1V2OUT, RSVD/VBG handling, and the ferrite-split analog rail all match it — and adds the line's standard 100 Ω series protection and on-module pull-ups. The highest-risk items are exactly the ones no schematic check can see: LQFP-48 assembly quality, an MDI pair swap, a wrong-CL crystal (the MPN is still TBD), and the ~130 mA draw against the host PMOD rail budget. VERSIONR = 0x04 is the single most valuable bring-up gate on the board; the autonegotiation matrix and the deferred chassis-split/EMC questions are the main open items after it. Nothing here has ever been powered.