← AXA-006

Circuit review & bench-test guide

AXA-006 — TMC2209 stepper driver PMOD module

Document purpose#

This document explains the axa-006-stepper PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py), the module README, the actuator-line rules in ../README.md, and the TMC2209 datasheet rev 1.09.

This is an unfabricated prototype design. Status at time of writing: schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, no board built, no first-article bench evidence of any kind. Every number below is a design target derived from the schematic and the datasheet, not a measurement. Several MPNs are still marked TBD in the design source (bulk capacitors, sense resistors, screw terminals). Nothing in this document proves that an assembled board is safe or functional.

Unlike the USB-C PD trigger guide this document has no QA ledger to cite; the honest count is 0 PASS, 0 FAIL, everything OPEN until a board exists.

1. What the board does#

The board is a soldered (deliberately not socketed) Trinamic/ADI TMC2209 two-phase stepper motor driver on the AruviX PMOD actuator-module outline. The FPGA host drives STEP/DIR for motion, ENN for enable, and the single-wire PDN_UART interface for register configuration (run/hold current, microstep resolution, stealthChop/spreadCycle, StallGuard4). Motor power (VS, 4.75–29 V) enters only on the J2 screw terminal; the PMOD carries 3.3 V logic exclusively, per the actuator-line rule. Grounds join on the module.

Defaults are standalone-legal: MS1/MS2 strapped to GND (UART address 0, 1/8 microstep in standalone), SPREAD to GND (stealthChop), CLK to GND (internal 12 MHz oscillator), STDBY to GND (always awake), ENN pulled up 10 k so the driver is disabled until the host actively drives ENN low. VREF is strapped to 2.5 V, which selects the full analog current scale of about 1.77 A rms with the fitted 0.11 Ω sense resistors — deliberately high, so that scaling the current down over UART (IRUN) is part of the curriculum and mandatory before running small motors.

Functional block diagram#

PMOD host (3.3 V logic only)                        Motor supply 4.75-29 V
J1 ──────────────────────────┐                      J2 screw terminal (VMOT)
  1 STEP ────────────────────┤                        │
  2 DIR ─────────────────────┤                        ├── C1,C2 2x22 uF bulk
  3 ENN ──[R1 10k pull-up]───┤                        ├── C3 100 nF
  4 DIAG ◄──[R2 100R]────────┤                        │
  7 UART_TX ──[R4 1k]──┐     │                        v
  9 UART_RX ◄─[R5 100R]┼─────┤ PDN_UART        ┌─────────────┐
  8 INDEX ◄──[R3 100R]─┘     │                 │  U1 TMC2209 │◄─ C4/C5 charge pump
  6/12 3V3 ──[C8]── VCC_IO ──┘                 │   VQFN-28   │── C6 5VOUT 4.7 uF
                                               └──┬───────┬──┘── R8/R9/C7 VREF=2.5 V
        JP1 MS1=GND  JP2 MS2=GND                  │       │
        (UART addr 0, 1/8 ustep)             OA1/OA2   OB1/OB2
                                                  │       │
                                     BRA ─[R6 0.11R]─ GND │
                                     BRB ─[R7 0.11R]─ GND │
                                                  v       v
                                          J3 MOTOR A   J4 MOTOR B

2. Safety and scope boundaries — actuators move#

This module differs from every power-only board in the family in one fundamental way: its output is a machine that moves and holds torque. The following rules are not generic boilerplate; each maps to a real failure mode.

• NEVER disconnect or connect motor leads while the driver is powered. This is the single most important stepper-driver rule and it deserves emphasis beyond the generic hot-plug prohibition: the motor phases are inductors carrying regulated current. Interrupting a phase circuit mid-conduction forces the inductor voltage to whatever value keeps the current flowing — an arc across the opening contact and a spike far beyond the TMC2209's 32/33 V absolute maximum. The datasheet's absolute- maximum footnote already warns that mere trace and sense-resistor stray inductance produces volts of ringing; an interrupted motor lead is that effect multiplied by the full phase inductance and kills the driver essentially instantly. Screw terminals (J3/J4) make casual re-plugging tempting; power VS down and wait for C1/C2 to discharge first, every time, no exceptions.
• First power-up must use a current-limited motor supply. Set the bench supply to the target VS with the current limit at or below roughly 0.5 A before any motor is connected, and raise it deliberately once behavior is verified. Typical NEMA17 motors are rated 1–2 A per phase; do not begin there.
• A stepper at standstill still draws full holding current. Unlike a DC motor, an enabled stepper that is "doing nothing" is regulating IHOLD through both phases and heating the motor, the sense resistors, and the driver continuously. "The motor isn't moving" never means "the circuit is idle." Disable via ENN (or verify standstill current reduction) before assuming anything is unpowered.
• Flyback / stored inductive energy. The TMC2209's integrated bridge MOSFET body diodes handle normal chopper recirculation; there are no external flyback diodes on this module and the datasheet does not require them. That protection assumes the circuit stays connected — see the hot-unplug rule above — and assumes VS bulk capacitance (C1/C2) is present to absorb energy returned to the rail during deceleration.
• Rail sequencing: logic before motor. Apply PMOD 3.3 V (VCC_IO) before VS, and remove VS before 3.3 V. The TMC2209 monitors VS, 5VOUT, and VCC_IO with internal undervoltage detectors and the datasheet does not demand a strict order, but its input-protection diodes clamp every logic pin to VCC_IO: driving STEP/DIR/UART into an unpowered VCC_IO domain back-powers the pin through the protection diode (10 mA absolute max per pin). With VCC_IO absent the ENN pull-up (R1, to 3V3) is also absent, so the enable state is defined only by the TMC2209's internal pull-up behavior — do not rely on it. Logic first, motor second; motor off first, logic last.
• "Hands clear" before the first commanded motion. Agree and announce before any STEP stream or UART velocity command is issued. A bare motor shaft is mostly harmless; the same motor on a lead screw, pulley, or belt can pinch fingers or drive a mechanism into a hard stop with full torque. Keep loose clothing, hair, and probe leads away from anything that can rotate, and do the first motion tests with the motor unloaded (nothing on the shaft).
• The 20 x 40 mm module has no fusing on VS. The bench supply current limit is the only overcurrent protection during bring-up; keep it set.
• Bench-only scope: no EMC, ESD, vibration, or safety certification is implied by anything in this document.

3. Power and control sequence#

1. PMOD 3.3 V arrives on J1 pins 6/12. C8 decouples VCC_IO; R1 pulls ENN to 3.3 V so the power stage is disabled by default.
2. VS arrives on J2. C1/C2/C3 hold up the rail; the internal 5 V regulator starts and charges C6 on 5VOUT (datasheet: 4.75 V minimum VS for the -LA part; internal UVLO releases at 3.5–4.6 V rising).
3. The charge pump (C5 flying, C4 reservoir to VS) generates the high-side gate supply; uv_cp in DRV_STATUS reports charge-pump undervoltage.
4. R8/R9 divide 5VOUT to 2.5 V on VREF (filtered by C7), selecting 100 % analog current scale. With MS1/MS2 = GND the standalone microstep resolution is 1/8 and the UART node address is 0.
5. The host configures the driver over PDN_UART (R4/R5 network): reduce IRUN/IHOLD first, then chopper/microstep settings as desired.
6. The host drives ENN low. The driver energizes the phases at IHOLD; the motor now holds position and draws current continuously.
7. STEP edges advance the internal sine table; DIR sets sign; INDEX pulses once per electrical rotation of the table; DIAG goes high on stall (StallGuard4) or driver error (cleared by ENN = high).

4. Interfaces and straps#

Per the TMC2209 datasheet MS2:MS1 straps select — GND:GND = 1/8 microstep, address 0; GND:VCC_IO = 1/32, address 1; VCC_IO:GND = 1/64, address 2; VCC_IO:VCC_IO = 1/16, address 3. The default build is address 0, 1/8.

There are no dedicated test points in the schematic yet (layout not started). The natural probe nodes are the J1 pins, J2/J3/J4 terminals, the VREF divider midpoint (R8/R9 junction), 5VOUT at C6, and the sense-resistor tops (R6/R7). Adding named test points for VREF, 5VOUT, PDN_UART, and both sense nodes is a layout-stage recommendation from this review.

5. Component-by-component review#

5.1 Driver and power/motor connections#

Swapping the two wires within one phase only reverses direction; swapping one wire between phases (e.g., OA2 and OB1) produces a motor that buzzes and does not rotate. Both are harmless to the driver if done unpowered.

5.2 Current sense and VREF network#

Datasheet notes applied here: VREF scales current linearly from 0 V to 2.5 V (I_scale_analog = 1, the default); 2.5 V or above equals the internal reference, i.e. 100 % scale. ADI recommends sizing sense resistors so the desired maximum current lands at VREF = 2.0–2.4 V for best precision; this board instead pins VREF at full scale and teaches current reduction through UART IRUN. That is a deliberate curriculum choice, but it means the board defaults to 1.77 A rms full scale, above the datasheet's 1.4 A rms continuous per-coil design guideline — reducing IRUN before sustained operation is not optional. The VREF pin input resistance (190–300 kΩ to an internal 1.8 V) loads the 5 k Thevenin divider by only about -15 mV; negligible.

5.3 Logic interface resistors and straps#

5.4 Capacitors#

X7R/X5R DC-bias derating applies to C1/C2: a 22 µF 1210 X7R at 24 V VS retains substantially less than nominal capacitance. The exact retained value must be checked against the chosen MPN's bias curve once the TBD is resolved; treat "2 x 22 µF" as the label, not the effective value.

6. Datasheet summary and design interpretation#

All TMC2209 figures below were taken from the datasheet rev 1.09 (2023-FEB-16) PDF: TMC2209 datasheet rev 1.09 (product page; the same rev 1.09 PDF is mirrored at mouser.com). The Bourns CRL sense-resistor reference cited by the design source is bourns.com/docs/Product-Datasheets/CRL.pdf (not independently verified here — the MPN is still TBD; confirm the 1206 size's pulse-power rating against the datasheet before ordering).

Values not found in the datasheet text during this review (and therefore to be confirmed directly against the PDF/errata before release): the maximum tolerated VS ramp rate, and any formal statement about motor-lead disconnection (the hot-unplug rule in section 2 is standard practice grounded in the abs-max/inductance footnote, not a quoted datasheet sentence).

7. Board-specific analyses#

7.1 VREF measurement to run-current math#

The board fits R_SENSE = 0.11 Ω (R6/R7) and straps VREF to 2.5 V. With the datasheet's internal 20 mΩ BRxy resistance added, at vsense = 0 (V_FS = 325 mV) and full current scale (standalone, or UART IRUN = 31, CS = 31):

I_rms(full scale) = (325 mV / (0.110 + 0.020) Ω) x (1/sqrt(2)) x (V_VREF / 2.5 V)
                  = (0.325 / 0.130) x 0.7071 x (2.5 / 2.5)
                  = 2.50 A peak-equivalent x 0.7071
                  = 1.768 A rms          (board docs round to 1.77 A)

With UART IRUN (CS = IRUN, 0–31) the current scales as (IRUN + 1)/32:

Bench procedure: measure VREF (R8/R9 junction) with a DMM before first enable. Expected 2.50 V nominal (2.44–2.56 V with 1 % resistors and 5VOUT tolerance; about 15 mV low from VREF pin loading). Then the actual phase current should be confirmed with a current probe or by measuring the mean sense-resistor voltage — the datasheet itself says to "measure and fine tune the current in the application" rather than trust the formula, and the stated tolerance is +/-2 % with external VREF at 2 V. All figures above are targets; none has been measured on hardware because no hardware exists.

7.2 The single-wire UART quirk: you always hear yourself#

PDN_UART is a half-duplex single wire. On this board host TX reaches the wire through R4 (1 kΩ) and host RX taps the wire through R5 (100 Ω) — the exact network in datasheet Figure 4.1. Consequences:

• Every byte the host transmits appears on its own RX. The datasheet states this outright ("all transmitted data also is received by the RXD input"). After a 4-byte read request the host receives 4 + 8 = 12 bytes: its own echo, then the reply. Firmware/HDL must discard the first 4.
• During the TMC2209's reply the host TX must idle high; the reply driver wins the wire because R4 limits what the idle-high TX can source into it. If the host actively drives during the reply window, the read is corrupted (and R4 is what prevents damage).
• The reply starts SENDDELAY (default 8 bit times) after the request and the TMC2209 releases the wire 4 bit times after its last stop bit.

Loopback verification (do this before blaming the driver): with the module unpowered or U1 absent, send any byte from the host and confirm the identical byte arrives on host RX via R4 -> wire -> R5. This proves the TX path, the RX path, and the echo handling in one step. Then, powered, send a read request and confirm 12 bytes total. A host that receives exactly its echo and nothing more has a working TX path but no driver reply — check power, address straps, baud rate, CRC, or R5.

7.3 IFCNT: the canonical bring-up test#

Register 0x02 (IFCNT, read-only, 8 bit) increments on every successfully received write datagram — correct sync, address, CRC — and wraps from 255 to 0. Read accesses do not change it. This makes the following loop the end-to-end proof of the UART link, and it requires no motor, no VS-side enable, and no motion:

1. Read IFCNT; record N.
2. Write any harmless register (e.g., write GCONF back with its current value, or set SENDDELAY in NODECONF at 0x03).
3. Read IFCNT again. Expect exactly N + 1 (mod 256).

If IFCNT increments, the entire chain works: host TX, R4, PDN_UART input, baud detection, addressing, CRC generation, plus the read path back through R5. If writes seem to succeed but IFCNT does not move, the write datagrams are being rejected — almost always CRC or node address. Do not proceed to motion until this test passes; a driver running on power-up defaults at IRUN = 31 (1.77 A) because its configuration writes were silently dropped is exactly the failure this test exists to catch.

7.4 Microstep smoke test#

After IFCNT passes and IRUN is confirmed reduced (read back IHOLD_IRUN or verify via measured phase current):

1. Motor connected (leads secured — see hot-unplug rule), shaft unloaded, hands clear, VS current-limited to about 0.5 A.
2. Set IRUN to 8 or below. Enable with ENN low. The motor should snap gently to a detent and hold; supply current settles to the IHOLD level.
3. Issue a slow STEP stream (e.g., 200 Hz at 1/8 microstep = 1/8 rev/s on a 200-step motor). Expect smooth, quiet, continuous rotation — stealthChop at low speed is nearly silent. Audible ticking once per full step, or shaft oscillation without rotation, indicates a wiring or microstep problem, not a tuning problem.
4. Invert DIR and confirm the direction reverses. Confirm INDEX pulses (once per electrical rotation, i.e. every four full steps) on PMOD 8.
5. Alternatively drive motion with UART velocity mode (VACTUAL, register 0x22) with STEP left idle — this exercises the internal step generator and proves the UART path can do more than configuration.
6. Watch DIAG throughout: it must stay low. DIAG high means stall or driver error; disable (ENN high, which also clears the error) and investigate before retrying.

8. Two bench contexts#

8a. PMOD host (AruviX ECP5 or other FPGA board)#

• The FPGA board supplies 3.3 V on J1; a separate current-limited bench supply feeds J2. Grounds join on the module by design — do not add a second ground bond between the motor supply and the FPGA board's supply unless a ground loop has been deliberately considered.
• Sequencing: power the FPGA board (3.3 V present, ENN pulled high) before VS, and configure the FPGA so STEP/DIR/UART_TX idle at defined levels (UART_TX idle high) before VS is applied. Power down in reverse order.
• The FPGA I/O bank must be 3.3 V (LVCMOS33). The TMC2209 VIH is 0.7 x VCC_IO = 2.31 V at 3.3 V — met with margin.
• Remember the VCC_IO UVLO ceiling (3.0 V max rising): a host 3.3 V rail that droops during FPGA configuration can reset the driver; re-send the UART configuration after any host reconfiguration.

8b. Standalone bench (no FPGA)#

• A bench 3.3 V logic supply feeds J1 pins 6/12 (return on 5/11), and a separate current-limited motor supply feeds J2. A 3.3 V USB-UART adapter drives the link: adapter TX to J1 pin 7 (UART_TX), adapter RX to J1 pin 9 (UART_RX), adapter GND to J1 GND. The board's R4/R5 network already implements the single-wire combining, so an ordinary two-wire adapter works; the adapter will see its own echo per section 7.2.
• The adapter must be a true 3.3 V-logic type. A 5 V adapter violates the VVIO + 0.5 V input limit.
• ENN (J1 pin 3) must be actively pulled low to enable — a jumper to GND is acceptable for bench work; remove it to disable. STEP/DIR may be driven from a function generator (3.3 V logic levels, DIR changes only while STEP is idle) or left low for UART-only bring-up.
• Grounding: three grounds meet at the module (logic supply, motor supply, USB-UART adapter, which is usually earth-referenced through the PC). Keep the motor-supply leads short and twisted; connect scope grounds to module GND only. Sequencing rule is unchanged: 3.3 V first, then VS.

9. Expected values before bench testing#

All values are design targets. No column of measured results exists yet.

10. Manual schematic and assembly review checklist#

• Confirm U1 pin-1 orientation and that the exposed pad (pin 29) has thermal-via stitching in the eventual layout; X-ray or pull-test the EP on first articles.
• Verify the three TBD MPNs (C1/C2 bulk, R6/R7 sense, J2–J4 terminals) are resolved, and check the sense-resistor pulse power and the bulk-cap DC bias curve against the choices.
• Measure R6 and R7 in-circuit before first power (expect ~0.11 Ω plus probe error; a 4-wire measurement is better). An open sense resistor is the single worst assembly fault on this board.
• Measure the R8/R9 divider: ~10 kΩ each, junction to be 2.5 V once powered.
• Confirm JP1/JP2 are bridged to GND (default build).
• Buzz J1 pin map against the table in section 4 — especially that 3V3 and GND land on 6/12 and 5/11 and that motor nets never touch J1.
• Confirm no continuity between VMOT and 3V3, VMOT and 5VOUT, or any motor phase and any J1 pin.
• Check C4 orientation of intent: it goes VCP-to-VMOT, not VCP-to-GND — a netlist-level check, easy to misread on layout.
• Kelvin-route the sense resistors in layout (called out as remaining work in the README); review before fab, not after.

11. Ordered bench-test procedure#

Stop at the first abnormal result. Record everything against the bench record template in section 13. Hands clear before any commanded motion.

A. Unpowered inspection and resistance tests#

1. No supplies, no motor, no host. Complete the checklist in section 10.
2. Measure resistance VMOT-to-GND (expect high, capacitor charging behavior), 3V3-to-GND, 5VOUT-to-GND, and each motor output to GND and to VMOT. Investigate any hard short before applying power.
3. Verify R6/R7 ~0.11 Ω, R8/R9 divider, R1 pull-up path, and the R4/R5 UART network by continuity.
4. Standalone context only: perform the unpowered UART loopback of section 7.2 (host byte echoes back through R4/R5).

B. Logic rail only#

1. Apply 3.3 V to J1 (current-limited, 100 mA is ample). No VS, no motor.
2. Confirm 3.3 V current draw is small and stable; ENN reads high; no part warms.

C. Motor rail, no motor#

1. With 3.3 V still present, apply VS (12 V recommended first, limit 0.2 A). J3/J4 empty.
2. Confirm 5VOUT ~5 V, VREF ~2.5 V, quiescent VS current modest and stable, DIAG low.
3. Perform the IFCNT test of section 7.3. Do not continue until it passes.
4. Write IHOLD_IRUN with IRUN = 8 (or lower) and IHOLD lower still; read back what the interface allows and re-verify IFCNT counted every write.

D. Motor attached, first enable (no motion)#

1. Power everything down. Wait for C1/C2 to discharge. Connect the motor to J3/J4 and torque the screw terminals properly.
2. Re-apply 3.3 V, then VS with the current limit at ~0.5 A. Re-send the UART configuration (it survives, but verify via IFCNT/read-back — any rail glitch during connection work resets it).
3. Drive ENN low. Expect the motor to hold; record standstill supply current. Nothing should get more than warm within two minutes.
4. Disable (ENN high) and confirm holding torque releases.

E. Motion smoke test#

1. Run the microstep smoke test of section 7.4 (low IRUN, slow STEP, both directions, INDEX and DIAG observed). Unloaded shaft only.
2. Raise the step rate gradually. Note any resonance bands and whether stealthChop remains quiet; a stall (shaft stops, DIAG may assert) at modest speed and low IRUN is expected physics, not necessarily a fault — log it with the IRUN and rate.

F. Current-accuracy and thermal characterization#

1. With a current probe (or sense-voltage measurement), verify measured phase current against the section 7.1 table at two or three IRUN settings. Record the deviation.
2. Step IRUN toward the motor's rating only as far as the test motor and the bench supply allow; never exceed 1.4 A rms continuously without a deliberate duty-cycle plan per the datasheet.
3. 30–60 minute soak at the intended working current: log U1, R6/R7, motor case, and terminal temperatures. There is no thermal estimate to compare against yet — this run creates the baseline.

G. Release-only tests#

StallGuard4 threshold characterization on a real mechanism, spreadCycle comparison, VS range extremes (4.75–5.5 V low end explicitly unverified, 29 V high end with ringing headroom measured), repeated-fault behavior, and the full HDL deliverable (step_profile, UART master with CRC8 and echo discard, self-checking testbenches) are release-gate work, not bring-up work.

12. Troubleshooting map#

13. Bench record template#

14. Review conclusion#

The schematic is a faithful implementation of the TMC2209 rev 1.09 standard application: charge pump, 5VOUT, decoupling, strap choices, and the single-wire UART network match the datasheet exactly, and the actuator-line rules (motor power only via J2, fault line on the PMOD, series protection on driver-driven pins) are all honored. The design's one deliberate sharp edge is the VREF-at-full-scale current strategy: the board powers up scaled for 1.77 A rms, above the datasheet's 1.4 A continuous guideline, and relies on the operator performing the UART IRUN reduction that the curriculum teaches. The IFCNT test exists precisely to guarantee that reduction actually landed before any motor sees current.

The principal open risks are: no PCB layout (EP thermal design and sense Kelvin routing are still unbuilt and thermally uncharacterized), three unresolved MPNs, the unverified 4.75–5.5 V low-VS claim, no fusing on VS, and — as with any stepper module — the operator-dependent hazards: hot-unplugged motor leads destroy the driver, and an enabled stepper holds current and torque even when nothing moves. No bench evidence exists yet; this guide defines what that evidence must look like.