Actuator modules

AXA-007 — STSPIN230 BLDC/FOC driver dual-PMOD module

Catalog #7 in the AruviX actuator line, level L5 — the line's flagship, and a dual-PMOD module like the camera (axs-050). STSPIN230 (ST): 3-phase driver for 1.8–10 V, 1.3 A rms gimbal/ drone-class small motors.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADC_SDO CS_N EN EN_FLT GND H1_RAW H2_RAW H3_RAW HALL1 HALL2 HALL3 INA_OUT INUH INUL INVH INVL INWH INWL MISO OUTU OUTV OUTW SCK SNS_P STBY VMOT VREF_MID

Production status#

Source: boards/actuator-modules/axa-007-bldc

Catalog #7 in the AruviX actuator line (../README.md), level L5 — the line's flagship, and a dual-PMOD module like the camera (axs-050). STSPIN230 (ST): 3-phase driver for 1.8–10 V, 1.3 A rms gimbal/ drone-class small motors.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches (the FOC ladder)#

1. Six-step hall commutation — read HALL1–3, table-commutate, spin.
2. Hall-FOC — Clarke/Park transforms, PI current loop closed through the shunt→INA240→ADS7042 chain at PWM rate, SVPWM back out. Hardware FOC at 20 kHz+ loop rate is the actuator-side FPGA-beats-MCU demo.
3. Sensorless — replace the halls with a back-EMF observer (later; the hall socket stays as the truth reference while you bring it up).

Design#

Drive (J1, PMOD A)#

• The STSPIN230 exposes SIX gate inputs (INxH/INxL per half-bridge), not the catalog sketch's "IN1–3" — documented deviation. The datasheet provides interlock protection, but commutation and dead time are still the fabric's job. J1 pins 1–3 = INUH/INVH/INWH, pins 7–9 = INUL/INVL/INWL.
• EN/nFAULT (J1 pin 4) is open-drain and bidirectional: 10 k pull-up on-module, 100 Ω series (line rule — it is driver-driven in the fault direction). The driver pulls it low on overcurrent/thermal fault; the host can also drive it low to kill the bridge. The fabric must watch it.
• STBY (J1 pin 10): STSPIN230 standby is entered with STBY low, so the 10 k pull-down keeps the power stage asleep until the host enables it — consistent with the line's default-off convention.
• Motor power VM 1.8–10 V on J2 screw terminal only; 2× 10 µF + 100 nF bulk. Phases OUTU/V/W on the J4 1x03 screw terminal. Grounds join here.
• Flyback: integrated bridge body diodes (line rule satisfied internally).

Sense (J3, PMOD B — Type 2 SPI positions + halls)#

• Single low-side shunt R10 = 0.05 Ω 1% 2512 in the SENSEU/SENSEVW return (both sense pins tie to the shunt top: one combined bus-current measurement; per-phase reconstruction from the active SVPWM vector is part of the L5 lesson).
• INA240A1 (20 V/V, enhanced PWM rejection — that feature is why this part: it holds its output flat while the bridge slews). REF1+REF2 tie to a 10k/10k mid-rail (1.65 V) so the output is bidirectional: zero current reads mid-scale, regen/decel reads below it. Chain gain: 50 mV/A × 20 = 1 V/A about 1.65 V.
• ADS7042 12-bit 1 MSPS SPI ADC (≈1.24 mA/LSB at 3.3 V full scale). Sample synchronous to the PWM valley — the fabric owns that timing, which is exactly why there is no MCU in this loop.
• Halls: 1x05 socket (3V3/GND/H1/H2/H3), 10 k pull-ups (open-collector halls) + 100 Ω series into J3 pins 7–9.

Deviation note: the task sketch placed the halls on PMOD A; they moved to PMOD B so all six timing-critical gate lines share one connector, and STBY took J1 pin 10 (the STSPIN230's six-input reality needs the pins).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (dual plugs on 0.9" centers per PMOD spec 1.2.0, Kelvin shunt routing), DRC, fab outputs
• [ ] hdl/: hall commutator → FOC core (Clarke/Park, PI, SVPWM) + ADS7042 SPI master, golden-model testbenches, ECP5 demo
• [ ] Pin shunt MPN, BOM export and availability check, design-review checklist