← AXA-009

Circuit review & bench-test guide

AXA-009 — WS2812 LED strip driver PMOD module

Document purpose#

This document explains the axa-009-ws2812 PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py), the module README, and the actuator-line family rules in ../README.md.

This board is an unfabricated prototype design. Repository status is "schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, not released." No board has been built, so there is no bench evidence of any kind: no timing capture, no thermal result, no connector current measurement. Every number below is a datasheet value or a design target to verify on the first article — none of it is proof that an assembled board works or is safe. Where a value depends on the unstarted PCB layout (trace widths, copper pours), this document says so explicitly.

1. What the board does#

The board is a single-channel WS2812/WS2812B addressable-LED strip driver in the AruviX actuator-module PMOD family (catalog #9, level L2). The host FPGA generates the 800 kHz single-wire WS2812 bit stream at 3.3 V on PMOD pin 1; one gate of a 74AHCT125 buffer, powered from the strip's 5 V rail, re-drives that stream at full 5 V logic levels. A 100 Ω series resistor damps the line at the strip connector. Strip power (5 V, potentially many amps) enters on a dedicated screw terminal and never flows through the PMOD connector — the same two-rail discipline every module in the actuator line follows.

The board contains no microcontroller, no regulator, and no protection devices: it is a level shifter with connectors. All intelligence (bit timing, frame latch, patterns) lives in the FPGA ws2812_tx HDL core (../../pmod-common/hdl/, not yet instantiated for this module per the README release checklist).

Functional block diagram#

PMOD host (3.3 V logic)                      external 5 V strip supply
        │                                             │
        v                                             v
   J1 PMOD plug                              J2 screw terminal 5V IN
   pin 1 DATA (3.3 V) ──┐                    1 V5_LED   2 GND
   pins 5/11 GND        │                        │
   pins 6/12 3V3        │        V5_LED ─────────┼──── C1 100n ── C2 10u ── C3 (DNP)
   (3V3 unused by U1)   │           │            │
                        v           v VCC(14)    │
                   U1 74AHCT125 gate 1           │
                   ~OE(1)=GND, A(2)=DATA         │
                        │ Y(3) = DOUT_BUF (5 V)  │
                        v                        │
                   R1 100R series damping        │
                        │                        │
                        v                        v
                   J3 strip terminal:  1 V5_LED  2 DOUT  3 GND
                        │
                        v
                   WS2812 strip (DIN of first LED)

   U1 gates 2-4: ~OE and inputs to GND, outputs drive low, left open.
   Grounds join on this module (PMOD GND = J2 GND = J3 GND).

2. Actuator-family safety and scope boundaries#

This module lives in the actuator line and inherits its safety discipline, adapted honestly: this board drives LED strips, not motors. Nothing here moves, pinches, or stores mechanical energy. The hazards are electrical and thermal, and they are real:

• The 5 V strip rail can carry many amps. A 144-LED strip at full white draws about 8.6 A (section 8). That is a wiring-gauge, connector-heating, and fire-risk problem, not a motion problem. Treat the V5_LED rail with the same respect the line gives motor rails.
• First power is always current-limited. Family convention: every first power-up uses a bench supply with the current limit set deliberately low (here: 0.5 A for a short test strip), raised only after behavior is verified. Never first-power from a fat "dumb" 5 V brick.
• Never hot-plug the strip while powered. Connecting or disconnecting a WS2812 strip with V5_LED live risks data-before-power at the first LED: the WS2812B absolute-maximum input rating is −0.5 V to VDD + 0.5 V, so a 5 V data edge arriving while the pixel's VDD pin is still bouncing through connector contact exceeds it. First-LED damage and latch-up from hot-plug is a well-known strip failure mode. Power down, connect, then power up.
• Data must not be driven into an unpowered strip. Same rating: if the FPGA streams data while the 5 V strip supply is off, U1 has no VCC either (it is powered from V5_LED), which is the design's built-in protection — but confirm U1's output really is inert in that state rather than assuming it (section 10, step B4). Do not "fix" this by powering U1 from 3V3.
• Rail sequencing. Preferred order: 3.3 V logic (PMOD host) may be up first with the data line idle low; then V5_LED; then start the data stream. Shutdown in reverse: stop data, drop V5_LED, then logic. Because U1's VCC is V5_LED, a 3.3 V-high DATA input while V5_LED = 0 V puts 3.3 V on an unpowered AHCT input; the SN74AHCT125 input absolute maximum is 7 V independent of VCC (inputs may exceed VCC), so this is within ratings — but keep DATA idle low across sequencing anyway as good practice.
• Other boards in this family DO move. If this module shares a bench, harness, or supply with motor/servo/stepper modules, the full family rules apply to the bench session: current-limited supplies, deliberate power-up order, hands clear of mechanisms, and an accessible way to kill power.
• Standard bench rules: scope ground only to board GND; this is a non-isolated logic board — do not connect it to anything mains-referenced; a working demo is not EMC, safety, or environmental qualification.

3. Power architecture and grounding#

The board has two rails and deliberately never connects them:

1. 3V3 (PMOD pins 6/12). Present on the connector per the PMOD standard but unused by any component on this module — U1 is not powered from it. It exists only because the PMOD plug template carries it. Verify at review that nothing was accidentally netted to 3V3.
2. V5_LED (J2 pin 1). The strip supply. It powers U1's VCC (pin 14), the decoupling network C1/C2 (and DNP C3), and passes through to J3 pin 1 for the strip. It never touches the PMOD connector — the one family rule that differs from the sensor line, applied here to LED power instead of motor power.

Grounds join on this module (PMOD GND pins 5/11, J2 pin 2, J3 pin 3 are one net). This is required: the WS2812 data signal is ground-referenced, so the FPGA, U1, and the strip must share a return. The consequence is that strip return current has a potential path through the PMOD ground pins if the external wiring is wrong. Correct wiring: the strip's heavy return current flows J3 GND → board → J2 GND → supply. The PMOD ground carries only logic-level currents. At layout time (not yet started) the J2–J3 ground copper must be sized for full strip current and the PMOD ground stitch kept out of that path.

Powering U1's VCC from V5_LED rather than 3V3 is a deliberate design choice with two effects: (a) the buffer output swings the full 5 V the strip wants, and (b) if the strip supply is absent, the buffer is dead and cannot drive data into an unpowered strip. Both must be confirmed on the bench.

4. Interfaces and pin maps#

No test points are defined in the current schematic. Until layout adds them, the practical probe points are: U1 pin 2 (DATA in), U1 pin 3 (DOUT_BUF), J3 pin 2 (DOUT after R1), U1 pin 14 (V5_LED), and J3 pin 3 (GND reference). Adding dedicated test points for these five nets is a recommended layout task.

5. Component-by-component review#

5.1 Level shifter and data path#

5.2 Power entry, decoupling, and connectors#

That is the complete bill: U1, R1, C1, C2, C3 (DNP), J1, J2, J3, and three schematic-only power flags. There is deliberately nothing else — no fuse, no reverse protection, no TVS. The review question is whether that is acceptable for a teaching module (see section 12).

6. Datasheet summary and design interpretation#

Official references: SN74AHCT125 datasheet (TI, SCLS264R), SN74AHCT125 product page, WS2812B datasheet (WorldSemi, Adafruit-hosted PDF), Yageo RC-series chip resistors. WS2812B timing has shifted between WorldSemi datasheet revisions (later revisions print different T0H/T1H nominals, e.g. 220–380 ns-class windows for T0H); the values above are from the revision cited. Check the revision that matches the actual strip's pixels before declaring a timing measurement out of spec, and check exact Murata/Phoenix orderables (two are still "TBD") before procurement.

7. Why the level shifter is needed — the one calculation that matters#

• WS2812B VIH(min) = 0.7 × VDD. At VDD = 5.0 V that is 3.5 V.
• A 3.3 V FPGA bank output can never exceed 3.3 V, and delivers less after I/O drop and cable loss. 3.3 V < 3.5 V: direct drive violates the datasheet minimum. It often "works" on the bench because real pixels switch below the guaranteed threshold — and then fails with temperature, strip batch, supply at 5.2 V (VIH becomes 3.64 V), or a longer lead.
• The 74AHCT125 fixes both directions of the mismatch: its TTL input threshold (VIH = 2.0 V) accepts 3.3 V with margin, and its 5 V-supplied output (VOH ≥ 3.94 V at full 8 mA load, ~5 V lightly loaded) drives the pixel with real margin above 3.5 V.

Bench verification (procedure step C): scope U1 pin 3 / J3 pin 2 and confirm logic-high ≈ 5 V (≥ 4.4 V acceptance with the strip attached), logic-low ≤ 0.4 V, and clean monotonic edges after R1 with no double transitions.

8. Strip current arithmetic and power-injection rule#

Budget 60 mA per pixel at full white (industry figure; confirm per strip vendor, section 6):

Compare against the board's ratings:

• Connectors: Phoenix MKDS 1,5 series is nominally a 13.5 A/1.5 mm² class part, so 30- and 60-LED full-white currents fit; 8.6 A approaches derated territory and the exact MPN is still "TBD" — confirm the ordered part's rating and use proper wire gauge (8.6 A wants ≥ 18 AWG, short runs).
• PCB traces: layout has not started; there is no trace rating to cite yet. The V5_LED and GND copper between J2 and J3 must be designed for the worst supported strip (recommend designing for ≥ 5 A continuous and documenting a hard limit on the silkscreen/README).
• Supply: the bench supply defines the real limit. Set its current limit to the planned test, never to its maximum.

Power-injection rule (from the design itself): on-module bulk cannot save a long strip — fit ≥ 470 µF external bulk at the strip head, and re-inject 5 V every ~100 pixels on big strips. Strip flex-PCB copper drops volts over a meter at amps; the symptom is white fading to orange/red toward the far end. Injected 5 V feeds must come from the same supply (or supplies with commoned grounds and matched voltage), and every injection point still shares the single data ground.

9. Manual schematic and assembly review checklist#

• Confirm U1 is exactly SN74AHCT125PW (AHCT, not HC/AHC/HCT variants with different thresholds or drive) and pin-1 orientation on the TSSOP-14.
• Buzz U1: pin 1 (1~OE) to GND; pin 2 to PMOD pin 1; pin 3 through R1 to J3 pin 2; pins 4, 5, 10, 9, 13, 12 to GND; pins 6, 8, 11 open; pin 14 to V5_LED; pin 7 to GND.
• Confirm nothing is netted to 3V3 except the PMOD connector pins.
• Confirm C3 is DNP in the core build; if populated, verify electrolytic polarity against the V5_LED/GND pads.
• Verify J2/J3 ordered MPNs and their current ratings (both "TBD" in the schematic today).
• At layout review (future): C1 at U1 pin 14; R1 at the J3 end of the trace; J2–J3 V5/GND copper sized per section 8; PMOD ground stitch out of the strip-current return path; test points added for DATA, DOUT_BUF, DOUT, V5_LED, GND.
• Confirm strip harness pinning: J3 1 → strip 5 V, 2 → strip DIN (not DOUT of the strip's first pixel), 3 → strip GND.

10. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, strip identity (vendor, pixel type, count), supply and scope IDs, and operator. First power uses a short strip (≤ 8 LEDs) or a single loose pixel, never the full-length strip.

Two host contexts are covered; steps note where they differ:

• Context P (PMOD host): module plugged into the FPGA board's PMOD; the FPGA supplies 3.3 V logic and drives DATA from the ws2812_tx core. Grounding: the FPGA board's GND and the strip supply's GND are joined on this module — connect the strip supply's return solidly to J2 pin 2 so strip current does not seek a path through the FPGA board's ground.
• Context S (standalone bench): a 3.3 V-swing function/pattern generator (or any 3.3 V GPIO source) drives PMOD pin 1, referenced to PMOD GND; a separate current-limited 5 V supply feeds J2. The two sources' grounds meet only on the module — do not add a second ground bond elsewhere, and set the generator to high-Z-load 3.3 V levels (a 50 Ω-terminated setting will halve the swing and may drop DATA below even the AHCT threshold).

A. Unpowered inspection and resistance tests#

1. No strip, no supplies connected. Complete the section 9 checklist under magnification; inspect the TSSOP-14 for bridges.
2. Measure V5_LED-to-GND resistance both meter polarities. Expect high resistance with a capacitive charging tail (C2); investigate any hard short before power.
3. Measure DATA-to-GND and DOUT-to-GND: no short; DOUT to DOUT_BUF should read ~100 Ω (through R1).
4. Verify the intended strip separately: correct DIN end identified, no visible damage, vendor current rating noted.

B. First power, no strip#

1. Context S first if equipment allows (fewer unknowns than a live FPGA). Set the 5 V supply to 5.00 V, current limit 100 mA. Do not connect J3 yet. Do not drive DATA yet.
2. Apply 5 V to J2. Expect quiescent current well under 1 mA (AHCT ICC max 20 µA plus capacitor leakage). Tens of milliamps or the limit tripping means a fault — stop.
3. Verify U1 pin 14 = 5 V, and DOUT_BUF/DOUT sit at a static logic level (DATA undriven floats only in context S — if so, expect possible indeterminate output and extra ICC; tie DATA low for this step).
4. Sequencing check: with 5 V removed and DATA driven high at 3.3 V, confirm DOUT stays near 0 V and the 3.3 V source current is negligible — the buffer must not deliver data into an unpowered strip rail.
5. Drive DATA with a 3.3 V 800 kHz square wave. Confirm DOUT toggles rail to rail at 5 V.

C. Level-shift verification (no strip or single pixel)#

1. Scope DATA (U1 pin 2) and DOUT (J3 pin 2) together, GND clip at J3 pin 3, ×10 probes, ≥ 100 MHz bandwidth.
2. Confirm DATA high ≥ 3.0 V at the pin (context P: an FPGA bank at 3.3 V; context S: generator into high-Z).
3. Confirm DOUT: high ≥ 4.4 V unloaded (≈ 5 V expected), low ≤ 0.4 V, monotonic edges, no double transitions or > 0.5 V plateau steps after R1. Overshoot beyond ~5.5 V at a connected pixel would threaten the WS2812B VDD + 0.5 V input rating — record it.
4. Record propagation skew DATA→DOUT (expect single-digit ns; anything in the hundreds of ns indicates probing or assembly error).

D. First-LED timing capture (short strip attached)#

1. Power down. Connect the short strip to J3 (5 V/DOUT/GND). Raise the current limit to 0.5 A. Power up (5 V first, then start data — per section 2 sequencing).
2. Drive a known pattern (e.g. alternating 0x00/0xFF frames) from the ws2812_tx core (context P) or a pre-programmed pattern source (context S).
3. Probe the data line at the first LED's DIN pad, referenced to the strip's GND at the same end. Measure and log against the WS2812B datasheet windows:

Measure at the WS2812B threshold levels (50% of 5 V is acceptable for pulse-width bookkeeping; note the method used). If the strip's pixels are a later WS2812B revision, pull that revision's windows before judging failure (section 6).

1. Confirm the pattern renders correctly on all LEDs of the short strip and that the frame latches (LEDs hold state during the ≥ 50 µs reset gap).

E. Load, thermal, and long-strip tests#

1. Step up strip length deliberately: 8 → 30 → 60 LEDs, resetting the supply current limit to the section 8 budget plus 20% each time.
2. At full white, log supply current versus the 60 mA/LED prediction, voltage at J2, at J3, and at the strip's far end (color shift toward red/orange at the far end = copper drop, apply the injection rule).
3. Feel-check then thermal-check J2, J3, and the J2–J3 copper after 10 minutes at full white. Screw-terminal temperature rise is the most likely first thermal finding.
4. 144-LED-class strips: only with power injection installed, wiring ≥ 18 AWG, connector rating confirmed, and the board's (future) layout current limit documented. Do not exceed whichever is lowest.
5. Re-verify first-LED timing (step D) at full load — supply droop and ground shift can move thresholds.

11. Expected values before bench testing#

12. Troubleshooting map#

13. Bench record template#

14. Review conclusion#

The design is minimal and coherent: one correctly chosen part does the one job the board has. AHCT is the right family for a 3.3 V-to-5 V single-wire shift — the TTL 2.0 V input threshold accepts the FPGA, and the 5 V-supplied output clears the WS2812B's 0.7 × VDD = 3.5 V requirement that makes direct 3.3 V drive out-of-spec. Powering U1 from the strip rail is a good implicit interlock against driving data into an unpowered strip. Unused gates are parked per the datasheet rule, decoupling is sensible, and the family's two-rail discipline (strip power never through the PMOD) is respected.

The principal open risks, all unverified because nothing has been built: no PCB layout exists, so every current-carrying claim (traces, ground return routing, C1 placement) is unproven; both screw-terminal MPNs are "TBD" with unconfirmed current ratings against an 8.6 A worst case; the board has no fuse or reverse-polarity protection, so bench discipline is the only protection layer; WS2812B timing windows vary by datasheet revision and must be matched to the actual pixels; the ws2812_tx HDL integration, testbench, and demo are still on the release checklist; and the 60 mA/pixel budgeting figure is an industry convention, not a number printed in the cited datasheet. First-article testing must start current-limited, with a short strip, and stop at the first abnormal result.