Comms modules

AXC-008 — USB low-speed soft-host lab PMOD module

Catalog #8 in the AruviX comms line, level L5 (2× GPIO). The famous "USB in pure fabric" project: a bit-banged USB 1.1 low-speed host (1.5 Mbit/s) built from nothing but a USB-A socket, resistors, and an ESD array. Zero-cost hardware, maximum bragging rights.

Level L5 ERC clean DRC clean Fab package 11 components

3D render of the AXC-008 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	VBUS HF decoupling at the socket	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	VBUS bulk for device inrush	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	USB-A	USB-A receptacle, THT horizontal, for the low-speed device under test	`67643-2910` Molex Datasheet ↗	`USB_A_Molex_67643_Horizontal`
`J3`	EXT 5V IN	External 5 V for device VBUS: 1 +5V, 2 GND (common with PMOD GND)	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal`
`R1`	68R	D- series element (bidirectional; sets source impedance both ways)	`RC0603FR-0768RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	68R	D+ series element	`RC0603FR-0768RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	15k	Host-side D- idle pull-down (USB LS: device's 1.5k on D- wins at attach)	`RC0603FR-0715KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	15k	Host-side D+ idle pull-down	`RC0603FR-0715KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R5`	0R	VBUS link (placeholder for a 200 mA polyfuse - none verified in stock libs)	`RC0603JR-070RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	USBLC6-2SC6	USB ESD protection array on D+/D-	`USBLC6-2SC6` STMicroelectronics Datasheet ↗	`SOT-23-6`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 DM_HOST DP_HOST EXT_5V GND USB_DM USB_DP VBUS

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/comms-modules/axc-008-usb-ls

Catalog #8 in the AruviX comms line (../README.md), level L5 (2× GPIO). The famous "USB in pure fabric" project: a bit-banged USB 1.1 low-speed host (1.5 Mbit/s) built from nothing but a USB-A socket, resistors, and an ESD array. Zero-cost hardware, maximum bragging rights.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

The whole LS host SIE in fabric: NRZI encode/decode, bit stuffing, CRC5/CRC16, SE0 keep-alives, SETUP/IN transactions, then HID report parsing from a real keyboard or mouse. The PS/2 module (axo-016) is the warm-up; usb_ls_host in pmod-common/hdl is the deliverable core.

Design#

USB-A receptacle: stock Connector:USB_A symbol + verified THT footprint Connector_USB:USB_A_Molex_67643_Horizontal (Molex 67643-2910).
D−/D+ to PMOD pins 1/2 through 68 Ω series elements (bidirectional source impedance; FPGA drives 0/1 to transmit, tristates to receive).
15 k pull-downs on both D lines on the connector side — the host-side idle state per USB LS; the device's own 1.5 k pull-up on D− overrides them to signal low-speed attach.
USBLC6-2SC6 ESD array (stock, verified) across D+/D− and VBUS.
VBUS: external 5 V screw terminal J3 → R5 0 Ω link → USB-A VBUS, with 100 nF + 10 µF at the socket. No polyfuse: no fuse/polyfuse footprint could be verified as the right stock part, so rev 1 uses the 0R link — replace with a 200 mA polyfuse at layout if one is qualified. GND is common with the PMOD. Never feed VBUS from the PMOD (3.3 V rail, ~100 mA budget).
3.3 V FPGA signaling on D± behind 68 Ω is the standard hobby-host arrangement for LS; noted in the schematic for the HDL lab text.

PMOD pin	1	2	3	4	5	6	7–10	11	12
Net	D− (68R)	D+ (68R)	NC	NC	GND	3V3	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (USB-A at the far edge, short matched D± stubs), DRC, fab
[ ] Qualify a 200 mA polyfuse to replace R5
[ ] hdl/: usb_ls_host bit-banged SIE + HID demo, golden-model testbench per the line release bar
[ ] BOM export and availability check, design-review checklist