Circuit review & bench-test guide

AXC-008 — USB low-speed soft-host lab PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axc-008-usb-ls, from generate_design.py, the module README.md, and the USB 2.0 low-speed signalling spec + USBLC6-2SC6 datasheet. Never fabricated; values are verification targets. This is the "USB in pure fabric" flagship — a resistors- and-ESD-only board; the entire serial interface engine lives in the FPGA.

1. What the board does#

Provides the physical layer for a bit-banged USB 1.1 low-speed (1.5 Mbit/s) host: a USB-A socket, D+/D− series resistors, host-side pull-downs, ESD protection, and an external 5 V VBUS. Everything else — NRZI, bit-stuffing, SYNC, packets, the SIE — is done in the FPGA. Enough to read a low-speed keyboard or mouse.

EXT 5V J3 ─> VBUS ─> J2 USB-A
J2 D+/D- ─> 68R series ─> PMOD 1 (D-) / 2 (D+) ; 15k pull-downs (host role)
U1 USBLC6-2SC6 ESD across D+/D-

2. Safety and scope boundaries#

Two rails: PMOD 3.3 V (logic), external 5 V (J3, VBUS for the device). The FPGA drives D+/D− at 3.3 V; USB low-speed thresholds are met (VIH of a bus-powered LS device is referenced to its own 3.3 V regulator, and the differential receiver works at 3.3 V drive — documented limitation, this is a lab not a compliant host).
VBUS current limit: set the bench supply feeding J3 to 5 V / 200 mA — no stock polyfuse is fitted (a 0 Ω link is used; the README flags replacing it with a 200 mA polyfuse at layout). A shorted device must not pull unlimited current.
Standalone: 3.3 V into 3V3/GND and 5 V/200 mA into J3.
Unreleased prototype; not a USB-compliant host.

4. Interfaces#

J1 PMOD Type 1: 1 D-_HOST, 2 D+_HOST, 5/11 GND, 6/12 3V3. Both are bidirectional bit-banged lines.
J2 USB-A receptacle (device plugs in here).
J3 external 5 V VBUS + GND.

5. Component-by-component review#

J2 USB-A receptacle: the device port. VBUS, D−, D+, GND. If VBUS is absent: a bus-powered device never enumerates (no power).
2× 68 Ω series (D+, D−): the USB-spec series termination between the FPGA and the connector. If absent: impedance mismatch, reflections corrupt the 1.5 Mbit signalling; also removes the current-limit on a driven line into a fault.
2× 15 kΩ pull-downs (D+, D−): define the host role. A low-speed device identifies itself by a 1.5 kΩ pull-up on D− (full-speed uses D+); the host holds both lines low through 15 kΩ until a device's pull-up wins, creating the idle "J/K" state and speed detection. If the pull-downs are absent: the host can't detect connect/disconnect or line state — the bus floats.
U1 USBLC6-2SC6 (SOT-23-6 ESD array): low-capacitance TVS on D+/D− (and VBUS). Hot-plugging a cable is an ESD event straight into FPGA pins. If absent: an ESD strike on insertion can damage the FPGA I/O — populate it. Its low capacitance (~few pF) doesn't distort 1.5 Mbit edges.
VBUS 0 Ω link (fuse placeholder): should be a 200 mA polyfuse; the 0 Ω link means the bench supply's current limit is your only protection — set it to 200 mA.
Decoupling 100 nF on VBUS: if absent: device inrush glitches the rail.

6. Datasheet / spec summary (USB LS)#

Low-speed: 1.5 Mbit/s, NRZI encoding, bit-stuffing (insert 0 after six 1s), SYNC field, differential D+/D−. Device attaches with a 1.5 kΩ pull-up on D− (LS). Host uses 15 kΩ pull-downs on both.
Idle "J" state for LS = D− high, D+ low. A single-ended-zero (SE0, both low) for ≥ reset time resets the device.
VBUS 5 V, ~100–150 mA for a keyboard/mouse. Enumeration = the host issues reset, then GET_DESCRIPTOR / SET_ADDRESS control transfers — all bit-banged here.
USBLC6-2SC6: 6 V standoff, IEC 61000-4-2 ±15 kV air ESD clamp, ~few-pF line capacitance.

7. Expected values before bench testing#

No device: both D lines low (15 kΩ pull-downs), VBUS 5 V present.
LS device attached: D− pulled to ~3 V by the device's 1.5 kΩ (idle "J"); the host FPGA can now detect connect.
Enumeration traffic: 1.5 Mbit NRZI packets on D+/D−.

8. Manual review checklist#

[ ] 68 Ω series on both D lines.
[ ] 15 kΩ pull-downs on both D lines (host role).
[ ] USBLC6 across D+/D−; VBUS decoupling.
[ ] VBUS protection = bench current limit (0 Ω link — set 200 mA).
[ ] Rails separate; 3.3 V and 5 V both present.

9. Ordered bench-test procedure#

A. Unpowered: verify 68 Ω series, 15 kΩ pull-downs, USBLC6 across the pair, VBUS path; no rail short.

B. Power, no device: 3.3 V, then 5 V/200 mA into J3. Confirm VBUS = 5 V at J2; both D lines low (pull-downs).

C. Connect detect: plug in a known LS device (cheap keyboard/mouse). Confirm D− rises to ~3 V (device 1.5 kΩ pull-up wins) → idle "J"; the host can now sense attach. Confirm VBUS current is within limit.

D. Reset + signalling scope: have the FPGA drive SE0 (both low) for the reset time, release; scope D+/D− for the 1.5 Mbit NRZI idle and the device's response. Confirm edges are clean through the 68 Ω/USBLC6.

E. Enumeration: run the fabric SIE: reset → GET_DESCRIPTOR(device) → expect the 18-byte device descriptor; SET_ADDRESS; GET_DESCRIPTOR(config). Capture the descriptor bytes as the success criterion.

F. Report data: for a keyboard, poll the interrupt IN endpoint; press a key; confirm the HID report byte changes. (This is the "it actually works" moment.)

10. Troubleshooting map#

No attach detected: 15 kΩ pull-downs missing, or VBUS absent (device unpowered).
Corrupted signalling: 68 Ω series missing (reflections), or USBLC6 wrong.
Nothing enumerates: the SIE timing in fabric (most likely — this board is just wires), or LS thresholds marginal at 3.3 V drive.
VBUS collapses: shorted device — the 200 mA bench limit protected you (fit a polyfuse for real use).

11. Bench record template#

Board: axc-008  VBUS: __ V  D lines idle low (no device): [ ]
Device attach: D- rises to __ V (idle J): [ ]
1.5Mbit NRZI on scope: [ ]
Device descriptor read (18 bytes): [ ]  HID report on keypress: [ ]
Notes:

12. Review conclusion#

The hardware is deliberately minimal — 68 Ω series, 15 kΩ host pull-downs, an ESD array, and VBUS. The pull-downs define the host role and the series resistors make the 1.5 Mbit edges survivable; the USBLC6 is non-optional given hot-plug ESD. Everything hard is in fabric. On the bench, the two proofs are attach-detect (D− rises via the device pull-up) and reading an 18-byte device descriptor. Keep VBUS at a 200 mA bench limit — the fuse is only a 0 Ω placeholder.