Lab modules

AXL-006 — Grove + Qwiic adapter PMOD module

Catalog #6 in the AruviX lab line, level L1. Opens the Seeed (Grove) and SparkFun/Adafruit (Qwiic/STEMMA QT) ecosystems — resolves the open ecosystem decision in the sensor-line README.

Level L1 ERC clean No fab package 13 components

3D render of the AXL-006 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Rail decoupling at the sockets	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Bulk for plugged Qwiic/Grove devices (within the 100 mA PMOD budget)	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	QWIIC 1	Qwiic / STEMMA QT socket: 1 GND, 2 3V3, 3 SDA, 4 SCL	`SM04B-SRSS-TB(LF)(SN)` JST Datasheet ↗	`JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal`
`J3`	QWIIC 2	Qwiic / STEMMA QT socket: 1 GND, 2 3V3, 3 SDA, 4 SCL	`SM04B-SRSS-TB(LF)(SN)` JST Datasheet ↗	`JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal`
`J4`	GROVE 1 I2C	Grove I2C socket (2.00 mm header stand-in): 1 SCL, 2 SDA, 3 VCC, 4 GND	not selected generic Datasheet ↗	`PinHeader_1x04_P2.00mm_Vertical`
`J5`	GROVE 2 GPIO	Grove GPIO socket (2.00 mm header stand-in): 1 D0, 2 D1, 3 VCC, 4 GND	not selected generic Datasheet ↗	`PinHeader_1x04_P2.00mm_Vertical`
`JP1`	SDA PULL-UP	Cut when a plugged Qwiic/Grove device already provides SDA pull-up	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP2`	SCL PULL-UP	Cut when a plugged Qwiic/Grove device already provides SCL pull-up	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`R1`	100R	Series protection on the Grove D0 line (either side may drive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection on the Grove D1 line (either side may drive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	4.7k	I2C SDA pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	4.7k	I2C SCL pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 D0 D1 GND G_D0 G_D1 SCL SCL_PU SDA SDA_PU

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	not run
Fab package	not exported
Fabricated	no — design stage only

Source: boards/lab-modules/axl-006-grove-qwiic

Catalog #6 in the AruviX lab line (../README.md), level L1. Opens the Seeed (Grove) and SparkFun/Adafruit (Qwiic/STEMMA QT) ecosystems — resolves the open ecosystem decision in the sensor-line README.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

Design#

2× Qwiic: JST SM04B-SRSS-TB horizontal — JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal is stock, verified. Standard Qwiic pinout: 1 GND, 2 3V3, 3 SDA, 4 SCL.
2× Grove: the Grove/HY-2.0 socket is confirmed not in the stock libraries (line review finding). The stand-in is a generic PinHeader_1x04_P2.00mm_Vertical footprint, which is pin-compatible with HY-2.0 sockets. Caveat: the footprint has no shroud outline — add a courtyard/silk rectangle for the socket body manually at layout, before DRC.
Grove 1 = I2C, Seeed pin order: 1 SCL, 2 SDA, 3 VCC, 4 GND.
Grove 2 = GPIO: 1 D0, 2 D1, 3 VCC, 4 GND; D0/D1 go to PMOD 7/8 through 100 Ω series resistors (either side may drive).
One shared I2C bus: both Qwiic sockets + Grove 1 + PMOD 3/4 (repeated on 9/10). One set of 4.7 kΩ pull-ups behind JP1/JP2 — cut when a plugged device already has pull-ups (most Qwiic boards do).
3.3 V only; 5 V Grove modules belong on AXL-005.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	NC	NC	SCL	SDA	GND	3V3	D0	D1	SCL	SDA	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout + manual Grove shroud courtyard/silk, DRC, fab outputs
[ ] Pin the HY-2.0 socket MPN (or promote a verified custom footprint)
[ ] BOM export and availability check, design-review checklist