← AXL-007

Circuit review & bench-test guide

AXL-007 — I2C hub PMOD module (TCA9548A)

Document purpose#

This document explains the axl-007-i2c-hub prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, and the TI TCA9548A datasheet.

The board is a design-stage prototype. The schematic is generated and ERC clean per reports/erc.rpt (2026-07-12: 0 errors / 0 warnings, with the standard ignored-check list) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended, I2C) module carrying a TI TCA9548A 8-channel bidirectional I2C switch. The upstream PMOD bus (SCL/SDA on pins 3/4, repeated on 9/10) fans out to mux channels 0–3, each terminated in a Qwiic socket (JST SM04B-SRSS-TB). Writing one control byte to address 0x70 connects any channel — or combination of channels — to the upstream pair, which resolves address clashes when a class chains many identical sensor modules: two same-address sensors on two channels is the canonical demo. Channels 4–7 are unconnected in rev 1 (four Qwiic sockets are what fits the 20 mm module outline).

Upstream pull-ups (4.7 kΩ, removable via solder jumpers JP1/JP2) follow the lab-line convention. Each downstream channel carries its own fixed 4.7 kΩ pull-up pair — a deselected mux segment is electrically floating and cannot borrow the upstream pull-ups; this is the schematic's stated lesson. ~RESET is host-driven directly on PMOD pin 2 with a 10 kΩ default-run pull-up (R11), so the hub runs unless the host deliberately resets it.

Functional block diagram#

PMOD J1                       U1 TCA9548A (TSSOP-24)
 2 RESET_N ──┬──────────────  ~RESET (pin 3)
             └─ R11 10k ── 3V3
 3/9  SCL ──┬── JP2 ── R2 4.7k ── 3V3     SCL ──┐ 8-ch switch, ctrl reg
 4/10 SDA ──┴── JP1 ── R1 4.7k ── 3V3     SDA ──┤ addr 0x70 (A0-A2 = GND)
 5/11 GND, 6/12 3V3 ── C1 100n, C2 1u ──  VCC = 3V3, GND
                                                │
   ch0: SD0/SC0 ── R3/R4 4.7k to 3V3 ── J2 Qwiic (1 GND, 2 3V3, 3 SDA, 4 SCL)
   ch1: SD1/SC1 ── R5/R6 4.7k to 3V3 ── J3 Qwiic
   ch2: SD2/SC2 ── R7/R8 4.7k to 3V3 ── J4 Qwiic
   ch3: SD3/SC3 ── R9/R10 4.7k to 3V3 ── J5 Qwiic
   ch4-7: SD4-7/SC4-7 no-connect (rev 1)

2. Safety and scope boundaries#

• The whole module — VCC, upstream bus, every downstream segment, and Qwiic power — lives on one 3.3 V rail. Never plug it into a 5 V PMOD host, and never wire a 5 V-driven bus segment into a Qwiic socket: the TCA9548A's I/O pins are 5 V tolerant, but every pull-up and every attached Qwiic device here is 3.3 V.
• The Qwiic sockets pass 3V3 straight through from the PMOD rail with no per-socket fuse or switch. The host's PMOD supply limit is the only protection; budget total downstream current accordingly.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~100 mA; the mux itself draws microamps, attached Qwiic devices dominate).
• Earth-referenced oscilloscope grounds clip only to board GND.
• The mux passes signals; it does not buffer, retime, or level-shift rise times. Total bus capacitance of the upstream segment plus every selected downstream segment must stay within the 400 pF I2C budget.
• A clean control-register readback proves the mux answers; it says nothing about the devices behind it or about signal integrity at 400 kHz with long Qwiic cables.

3. Power and control sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11; C1 (100 nF) decouples U1 and C2 (1 µF) provides module bulk.
2. The TCA9548A's internal power-on reset holds it in reset until VCC passes V_PORR (1.2 V typ, 1.5 V max). Registers and the I2C state machine then initialize to all zeroes: the control register reads 0x00 and all eight channels are deselected at power-up (datasheet Section 7.4.2). Every downstream segment sits isolated, held at 3V3 by its own pull-up pair.
3. A0–A2 are hardwired to GND, so the device answers at 7-bit address 0x70 (1110000b). There are no address straps on this board.
4. ~RESET idles high through R11 (10 kΩ). The host may drive PMOD pin 2 low (≥6 ns) at any time: registers and state machine reset, all channels deselect, and a stuck SDA is released within 500 ns (datasheet 7.4.1, 5.7/5.8). If the host leaves pin 2 floating, R11 keeps the hub running.
5. The host writes a single control byte — no register pointer exists — where bit n enables channel n. It then addresses downstream devices as if they were alone on the bus. Reading one byte from 0x70 returns the control register.
6. Deselecting (write 0x00) or resetting returns every segment to its isolated, pulled-up idle state.

4. Interfaces and pin maps#

Qwiic sockets (all four identical; standard Qwiic pinout):

U1 connections actually used (TSSOP-24 pin numbers per datasheet Table 4-1): A0/A1/A2 (pins 1/2/21) = GND, ~RESET (3) = RESET_N, SD0–SD3/SC0–SC3 (4–11) = channels 0–3, GND (12), SD4–SD7/SC4–SC7 (13–20) = no-connect, SCL (22), SDA (23), VCC (24) = 3V3.

I2C address strap review (datasheet Table 7-1 vs this board):

So exactly one AXL-007 can sit on an upstream bus (a second hub would clash at 0x70 unless placed behind a channel of the first — legal, but untested). The 0x70–0x77 range also collides with some Qwiic devices (e.g. other muxes, some LED drivers); keep such parts downstream, never upstream.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

Note there are deliberately no jumpers on the downstream pull-ups (R3–R10). If a Qwiic device that carries its own pull-ups (common; often 2.2 kΩ) is attached, the segment's effective pull-up drops to ~1.5 kΩ and the upstream-plus-segment total when selected approaches the 3 mA I2C sink budget. One device per channel is the design intent; daisy-chaining several pull-up-equipped Qwiic boards on one channel needs a pull-up audit.

6. Datasheet summary and design interpretation#

Consulted: TI TCA9548A datasheet SCPS207H (May 2012 – revised September 2024), <https://www.ti.com/lit/ds/symlink/tca9548a.pdf>, product page <https://www.ti.com/product/TCA9548A>.

Check the latest datasheet revision before procurement.

7. Expected values before bench testing#

Targets assume VDD = 3.300 V and address 0x70. All are design targets, not measured results.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin 1 = A0, adjacent to the ~RESET pin 3 corner) and the PWR suffix (TSSOP-24/PW).
• Verify A0, A1, A2 (pins 1, 2, 21) all land on GND — the address is hardwired, so a lifted pin silently moves the device to 0x71–0x74.
• Verify JP1/JP2 are bridged for a single-module build.
• Measure R1/R2 = 4.7 k from SDA/SCL to 3V3; R3–R10 = 4.7 k from each Qwiic pin 3/4 to 3V3; R11 = 10 k from RESET_N to 3V3.
• Buzz PMOD pins 3-to-9 (SCL) and 4-to-10 (SDA) — they are paired nets.
• Check each Qwiic socket's pin 1 is GND and pin 2 is 3V3 (a mirrored footprint powers attached devices backwards).
• Confirm SD4–SD7/SC4–SC7 (U1 pins 13–20) are genuinely unconnected — no accidental bridges to the channel 0–3 nets on the 0.65 mm-pitch TSSOP.
• Check C1 placement close to U1 pin 24 during layout review (layout not yet started — carry forward).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, bus speed, measured VDD, and the identity of every attached Qwiic device.

A. Unpowered inspection and resistance tests#

1. Complete the checklist above under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate < 1 kΩ.
3. Confirm SDA, SCL, and all eight SDn/SCn pins each read ~4.7 kΩ to 3V3, RESET_N reads ~10 kΩ to 3V3, and no signal is shorted to a neighbor or to GND.

B. First power, no I2C traffic, no Qwiic devices#

Context (a) — PMOD host: plug into a 3.3 V PMOD port on the ECP5 host (ULX3S-class) with the FPGA unconfigured. Context (b) — standalone: wire 3V3/GND from a current-limited bench supply and SDA/SCL from a 3.3 V lab adapter (Raspberry Pi Pico, FT2232H, Bus Pirate — I2C mode); leave RESET_N open (R11 holds it high) or wire it to an adapter GPIO for Section 9.G.

1. Supply current in the microamp band; SDA, SCL, RESET_N, and all eight downstream SDn/SCn pins sit at 3.3 V. A downstream pin at 3.3 V with all channels off is the per-channel pull-ups doing their job.
2. Measure VCC at U1 pin 24.

C. Control-register bring-up (exact bytes)#

Bus speed 100 kHz for bring-up. Address 0x70 means write byte 0xE0 and read byte 0xE1 on the wire. The TCA9548A has a single control register and no register pointer: a write is address + one data byte, a read is address + one returned byte — nothing else.

1. Power-up readback. S 0xE1 [byte] P. Expect 0x00 — all channels deselected, per the power-on reset. An ACK on 0xE1 at all is the first pass criterion; NACK means solder or address trouble (A0–A2 are hardwired, so there is no strap to check — go to U1 pins 1/2/21).
2. Channel walk with readback. For each pattern, write then read:

Every readback must echo the write exactly. 0x10–0x80 are register-only checks here: the register accepts them, but the switch outputs go to unconnected pins (rev 1). Multi-select (0x03 and similar) is legitimate only for broadcasting writes to identical devices — reading two same-address devices at once corrupts data (both drive SDA); see 9.H.

1. Finish with S 0xE0 0x00 P and confirm 0x00 back.

D. Per-channel bus scan with one device#

1. Attach one known-good Qwiic device (e.g. an AXS-line sensor module) to J2. With the control register at 0x00, scan the upstream bus: only 0x70 ACKs — the device is invisible.
2. Write 0xE0 0x01, rescan: the device's address now ACKs alongside 0x70.
3. Write 0xE0 0x02 (wrong channel), rescan: the device disappears again.
4. Move the device to J3, J4, J5 in turn and repeat with 0x02/0x04/0x08. Each socket must make the device appear only under its own bit.

E. Downstream isolation with two same-address devices#

This is the board's reason to exist. Use two devices with the same I2C address whose readings can be told apart — e.g. two AXS-032 ADS1115 modules both strapped 0x48, one with AIN0 grounded and one with AIN0 on a divider, or two identical temperature sensors with one warmed.

1. Device A on J2 (channel 0), device B on J3 (channel 1). Control register 0x00: scan shows neither ACKs at 0x48; only 0x70 answers.
2. S 0xE0 0x01 P: scan shows 0x48. Read the distinguishing value — it must match device A (e.g. the grounded-input reading).
3. S 0xE0 0x02 P: scan again shows 0x48 — same address, but the reading must now match device B. The same address answering with physically different data under different control bytes is the pass criterion.
4. S 0xE0 0x00 P: neither device ACKs at 0x48 again.
5. Negative test: S 0xE0 0x03 P (both channels), then attempt a read at 0x48 — expect corrupted/ANDed data or an analyzer error, never trust it. This demonstrates why multi-select reads of clashing addresses are illegal; a broadcast write (e.g. the same config to both ADCs) is the one legitimate multi-select use with clashing addresses.

F. Per-channel pull-up and low-level checks#

Upstream pull-ups are R1/R2 behind JP1/JP2; every downstream segment has fixed R3–R10. No segment on this board relies on the attached device's pull-ups — the fixed pairs guarantee a defined idle even with bare-die-style modules attached.

1. Unpowered, jumpers bridged: each channel's SDA/SCL (Qwiic pins 3/4) to 3V3 reads ~4.7 kΩ; upstream SDA/SCL likewise ~4.7 kΩ.
2. Unpowered, JP1/JP2 cut (do this once, deliberately, then re-bridge): upstream SDA/SCL to 3V3 goes open (megohms); the downstream readings do not change — proving the downstream pull-ups are jumper-independent. Re-bridge and re-verify ~4.7 kΩ before proceeding.
3. Powered, channel 0 selected, host driving SDA low at 100 kHz: scope upstream SDA and J2 pin 3 together. The downstream low sits above the upstream low by I × R_ON — expect ~10–20 mV at ~1.4 mA (bare segment). Both lows must stay below 0.4 V. Repeat per channel.
4. With a pull-up-equipped Qwiic device attached, recompute the sink current (Section 7 table); if the combined pull-up drops below ~1.1 kΩ, document it — the design intent is one device per channel.

G. Stuck-bus isolation and ~RESET recovery (deliberate fault)#

The mux's ability to fence off a hung segment is a feature; test it on purpose.

1. All channels off. Short J2 pin 3 (SD0) to GND through a 100 Ω resistor — a simulated device holding SDA low. Upstream scan still works and 0x70 still ACKs: the fault is invisible while channel 0 is deselected.
2. S 0xE0 0x01 P: upstream SDA is now held low through the switch. The bus is hung — the mux itself can no longer be addressed (no START can form). Confirm the adapter reports bus-busy/timeout.
3. Recover via ~RESET: pulse PMOD pin 2 low (any pulse ≥ 6 ns; a GPIO or a momentary jumper to GND through the 10 kΩ source impedance of R11 is fine). Upstream SDA must release within 500 ns; the control register reads 0x00; a scan works again with the fault still physically present on the (now deselected) segment.
4. Context (a): drive PMOD 2 from an FPGA GPIO — this is the reset line the eventual HDL lab must own. Context (b): if the adapter has no spare GPIO, a power cycle is the fallback recovery; note it in the record.
5. Remove the short; verify channel 0 works again (Section 9.D step 2).

H. Multi-select, speed, and host-integration tests#

1. Broadcast-write demo: two identical devices on channels 0/1, control register 0x03, one configuration write — then select each channel alone and confirm both devices took the config. Reads stay single-channel.
2. 400 kHz fast-mode regression of 9.C–9.E, with the longest intended Qwiic cables attached: multi-select adds every selected segment's capacitance to the upstream bus, so check rise times against the 400 pF budget at 0x0F (all four channels — the worst legitimate case on this board).
3. In the PMOD-host context, run the eventual I2C-master + mux-select HDL lab against Sections 9.C–9.E as its acceptance test.
4. Temperature, EMC, and long-cable characterization are out of scope for the first article.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design applies the TCA9548A's application guidance directly and gets the one non-obvious requirement right: fixed pull-up pairs on every downstream segment, because a deselected pass-gate segment floats and the switch itself cannot pull anything high. The hardwired 0x70 address, the host-driven ~RESET with a default-run pull-up (making stuck-bus recovery a first-class, testable path), and the register-only handling of the unconnected channels 4–7 are all coherent with the single-rail 3.3 V lab-line architecture. No discrepancy was found between the README and the generated schematic.

The principal open risks are that no PCB exists yet (layout, TSSOP-24 escape, and Qwiic socket orientation unverified), the single hardwired address (one hub per bus, and 0x70 collides with other mux-family Qwiic parts), the unfused 3V3 pass-through to four hot-pluggable sockets, pull-up stacking when attached Qwiic devices carry their own resistors (the combined sink current approaches the 3 mA I2C budget), and the fact that every expected value in this guide — including all control-register behavior — is taken from the datasheet rather than measured on hardware.