I/O modules

AXO-002 — 4-digit 7-segment direct-scan dual-PMOD module

Catalog #2 in the AruviX output line, level L2 (GPIO ×12, multiplexed). A Kingbright CA56-12SEKWA 4-digit common-anode display with no controller chip on purpose — the FPGA scans the digits itself. Needs both adjacent host PMOD sockets, like the camera module.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 DIG1 DIG1_A DIG1_G DIG2 DIG2_A DIG2_G DIG3 DIG3_A DIG3_G DIG4 DIG4_A DIG4_G GND SEG_A SEG_A_K SEG_B SEG_B_K SEG_C SEG_C_K SEG_D SEG_DP SEG_DP_K SEG_D_K SEG_E SEG_E_K SEG_F SEG_F_K SEG_G SEG_G_K

Production status#

Source: boards/io-modules/axo-002-7seg

Catalog #2 in the AruviX output line (../README.md), level L2 (GPIO ×12, multiplexed). A Kingbright CA56-12SEKWA 4-digit common-anode display with no controller chip on purpose — the FPGA scans the digits itself. Needs both adjacent host PMOD sockets, like the camera module (../../sensor-modules/axs-050-camera/).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Display multiplexing with nothing between the FPGA and the segments: the seg7_scan core drives one digit at a time at ~1 kHz refresh, and per-digit duty cycle gives dimming. Persistence of vision, refresh timing, and ghosting are all directly observable — that is the curriculum, not a nuisance.

Design#

• CA56-12SEKWA (stock symbol Display_Character:CA56-12SEKWA, stock footprint Display_7Segment:CA56-12SEKWA): 12 pins — 8 segment cathodes (A–G, DP) shared across digits, 4 per-digit common anodes.
• Everything is active-low. Common anode means a segment lights when its cathode is pulled LOW: the FPGA sinks segment current through the 220 Ω ballast resistors (J1). A digit lights while its P-FET gate is driven LOW (J3).
• Digit anodes switch through 4× AO3401A P-FET high-side switches (SOT-23): source → 3V3, drain → digit anode, gate ← 1 kΩ from PMOD B, plus 10 kΩ gate pull-ups to 3V3 so all digits stay off until the host drives them — an unconfigured FPGA shows a blank display, not garbage.
• Worst case ~8 segments × ~10 mA through one digit FET; the pins only ever sink one segment each (~10 mA peak, 1/4 duty), within ECP5 I/O limits.
• 100 nF rail decoupling at the switches; PWR_FLAGs on 3V3/GND.

Scan recipe: drive one DIGn low, present that digit's segment pattern on SEG_* (low = lit), rotate every ~250 µs (~1 kHz per digit).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (dual-plug spacing must match the host PMOD pitch — same constraint as axs-050), DRC, fab outputs
• [ ] hdl/: seg7_scan core (N-digit multiplexer + hex decoder), testbench, counter/clock demos
• [ ] BOM export and availability check, design-review checklist