I/O modules

AXO-007 — VGA output dual-PMOD module

Catalog #7 in the AruviX output line, level L4. The classic FPGA rite of passage: video timing from scratch, then a character generator, then a framebuffer — a keystone of the standalone-computer goal.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 BLU0 BLU1 BLU2 BLU3 GND GRN0 GRN1 GRN2 GRN3 HS HS_OUT RED0 RED1 RED2 RED3 VGA_B VGA_G VGA_R VS VS_OUT

Production status#

Source: boards/io-modules/axo-007-vga

Catalog #7 in the AruviX output line (../README.md), level L4. The classic FPGA rite of passage: video timing from scratch, then a character generator, then a framebuffer — a keystone of the standalone-computer goal.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Video timing generation (vga_timing HDL core — parameterized mode generator): 640×480@60 wants 25.175 MHz, and the ECP5's 25 MHz oscillator is inside stock monitor tolerance. Progression: color bars → character generator (chargen font ROM terminal) → framebuffer. With 4:4:4 color: 4096 colors, Pong/breakout with the joystick module (axo-013).

DAC design and the math#

Each color is a 4-bit binary-weighted resistor DAC driven by 3.3 V CMOS outputs, summing into the monitor's 75 Ω termination:

• Values (E96, 1%, 0603): bit 3 = 511 Ω, bit 2 = 1.02 kΩ, bit 1 = 2.05 kΩ, bit 0 = 4.12 kΩ (each ×2 the previous — binary weighting).
• All bits high → Thevenin equivalent: Req = 511 ∥ 1020 ∥ 2050 ∥ 4120 = 272.6 Ω, Veq = 3.3 V.
• Full-scale at the connector: Vfs = 3.3 V × 75 / (75 + 272.6) = 0.711 V ≈ the 0.7 V VGA full-scale spec (1.6 % high — invisible).
• One LSB = 0.711/15 = 47 mV. Per-bit contribution scales exactly ×2 because all four resistors share the same summing node and load.

Note: the catalog line suggested "E96 512R"; 512 Ω is not an E96 value — the E96 value is 511 Ω (Yageo RC0603FR-07511RL), a 0.2 % deviation, absorbed in the 1 % tolerance budget.

HS/VS are 3.3 V CMOS through 100 Ω series resistors; monitors accept 3.3 V sync levels.

Connector and ESD#

• Connector:DE15_Socket_HighDensity_MountingHoles (stock symbol) + Connector_Dsub:DSUB-15-HD_Socket_Horizontal_P2.29x2.54mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm (stock footprint), Amphenol L77HDE15SD1CH4F.
• DE-15 grounds (5–8, 10) and the shield (SH) tie to GND. Pins 4/9/11 NC.
• DDC (pins 12/15) unwired: no EDID; monitors fall back to analog-timing detection. Documented limitation.
• ESD: the cable is human-handled. Protection budget = the ladder's ≥273 Ω to any FPGA pin plus the ECP5 host socket's 200 Ω + clamps (PMOD spec 1.2.0). No stock 6-channel 75 Ω-video TVS array exists in the KiCad libraries, so a dedicated video ESD array is deferred to a layout-stage part pick (noted on the schematic).

PMOD pin map (dual socket, 0.9" centers — same constraint as axs-050)#

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (ladder resistors tight at the connector, 75 Ω-ish trace discipline on R/G/B, dual plugs on 0.9" centers), DRC, fab outputs
• [ ] hdl/: instantiate vga_timing + color-bar and chargen demos
• [ ] Layout-stage video ESD array part pick
• [ ] BOM export and availability check, design-review checklist