← AXO-009

Circuit review & bench-test guide

AXO-009 — buzzer pack (active + passive) PMOD module

Document purpose#

This document explains the axo-009-buzzer prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, the ERC report in reports/erc.rpt, and the Alpha & Omega AO3400A datasheet.

Prototype caveat — read first. This is an unfabricated prototype. The schematic is generated, ERC is clean (0 errors / 0 warnings, reports/erc.rpt), and the netlist has been reviewed. There is no PCB layout, no fabrication, no assembly, no BOM export, and no bench result of any kind. Two of the most important parts — the active buzzer BZ1 and the passive piezo BZ2 — are TBD: only the KiCad footprints are chosen (MagneticBuzzer_Kobitone_254-EMB84Q-RO and Buzzer_12x9.5RM7.6); the exact orderable MPNs are open. Every expected value below is a design target, not a measurement. Acoustic output and current draw depend entirely on the specific buzzers eventually chosen, so the sound-pressure and current numbers here are order-of-magnitude placeholders to be replaced once real parts are pinned.

1. What the board does#

The board is a 12-pin Type 1 GPIO PMOD carrying two independent sound channels, and the contrast between them is the lesson:

• Active channel (BZ1): an active magnetic buzzer with a built-in oscillator. Drive BUZZ_ACT to a steady logic high and it beeps at its fixed factory pitch. This is the on/off lesson — alarms and status beeps. The host does not, and should not, generate a tone; a DC level is the whole interface.
• Passive channel (BZ2): a passive piezo disc with no oscillator inside. Here the FPGA is the oscillator: a PWM square wave on BUZZ_PWM sets the pitch (frequency) and, loosely, the loudness (duty). This is the melody/siren/DDS-timing lesson. A steady DC on this channel does nothing but a single click.

Each channel is a low-side AO3400A N-FET switch: the load's high side ties to 3V3, its low side to the FET drain, and the source to GND. A 1 kΩ gate series resistor and 10 kΩ gate pull-down keep the FET off (and the buzzer silent) until the host actively drives the line. The inductive magnetic buzzer gets a flyback diode (D1); the capacitive piezo gets a bleed resistor (R5) instead — the difference in load type drives the difference in protection.

Functional block diagram#

PMOD J1 (Type 1 GPIO)
                     ACTIVE CHANNEL (on/off)
 pin1 BUZZ_ACT ──R1 1k──┬── BUZZ_ACT_G ──┤ Q1 gate (AO3400A)
                        │                 │
                    R2 10k             Q1 drain = ACT_SW
                        │                 │
                       GND      3V3 ──[ BZ1 active buzzer ]── ACT_SW
                                          │  (coil, self-oscillating)
                                 3V3 ──|<── D1 1N4148WS ──── ACT_SW
                                       (cathode to 3V3, flyback clamp)
                                          │
                                     Q1 source = GND

                     PASSIVE CHANNEL (PWM = pitch)
 pin2 BUZZ_PWM ──R3 1k──┬── BUZZ_PWM_G ──┤ Q2 gate (AO3400A)
                        │                 │
                    R4 10k             Q2 drain = PZ_SW
                        │                 │
                       GND      3V3 ──[ BZ2 passive piezo ]── PZ_SW
                                          │  (capacitive disc)
                                 3V3 ──[ R5 1k bleed ]────── PZ_SW
                                          │  (discharge path, NO diode)
                                     Q2 source = GND

 pins 5/11 GND   pins 6/12 3V3   C1 100nF rail decoupling
 pins 3,4,7,8,9,10 = NC

2. Safety and scope boundaries#

• This is a 3.3 V logic-level module. Both BUZZ_ACT and BUZZ_PWM are host-driven inputs to the FET gates; the module never drives the host, so the 100 Ω module-driven-line rule does not apply here (documented in the README).
• Acoustic hazard is low but real. A piezo swept near its ~4 kHz resonance at full drive is loud and shrill at close range. Do not press the disc to your ear; keep bench sweeps short.
• Use a current-limited 3.3 V bench supply for standalone testing. Set the limit modestly (e.g. 100–200 mA) until the real buzzers are pinned and their actual current is known — an active magnetic buzzer can pull tens of mA continuously.
• Earth-referenced oscilloscope grounds clip only to board GND. The flyback measurement in §9 looks at the Q1 drain (ACT_SW), which is a low-side node referenced to GND — safe for a standard probe.
• Do not drive the active buzzer with a PWM expecting a tone, and do not drive the passive piezo with steady DC expecting sound. Both are functional misuse (see §9-C); neither damages the board but both waste bench time.
• Because BZ1/BZ2 are TBD parts, treat their current, coil inductance, and capacitance as unknown until datasheets exist. Verify the chosen active buzzer's rated current is within the PMOD 3V3 budget before relying on it.
• Clean beeps are not an EMC, acoustic-emission, or product-safety qualification. This is a learning module, not a certified product.

3. Power and control sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11. C1 (100 nF) decouples the rail local to the two FET switches.
2. At power-up with the host tri-stated, R2 and R4 pull both gates to GND, so Q1 and Q2 are off. ACT_SW and PZ_SW sit at ~3V3 (pulled up through the buzzer / bleed resistor), and both buzzers are silent by default. This is the intended state for an unconfigured FPGA.
3. Active beep: the host drives BUZZ_ACT high. Current flows through R1 into Q1's gate; Q1's gate reaches ~3.3 V (well above the AO3400A threshold), Q1 turns on, and ACT_SW is pulled toward GND. Current flows through BZ1's coil; BZ1's internal oscillator drives the coil and it beeps at its fixed pitch. Driving the pin high is the entire action — there is no tone to generate.
4. Active stop: the host drives BUZZ_ACT low (or tri-states it, letting R2 pull it down). Q1 turns off. The coil current collapses; D1 clamps the inductive turn-off spike at ACT_SW to about 3V3 + one diode drop.
5. Passive tone: the host applies a PWM square wave on BUZZ_PWM (e.g. 4 kHz, ~50% duty). Q2 switches PZ_SW on and off at the PWM rate. The piezo disc is charged and discharged each cycle, flexing mechanically — the PWM frequency is the pitch. R5 provides the discharge path each time Q2 is off so the disc does not stay DC-biased.
6. Passive stop: the host drops the PWM to a static level. With Q2 off, R5 bleeds any residual charge off the disc and it goes silent (a static high or low produces at most a single click, not a tone).

Why the two channels are built differently#

The active buzzer is an inductive coil with its own driver; the passive piezo is a capacitive disc driven by the FPGA. An inductor resists a sudden current change and produces a large voltage spike at turn-off — hence D1. A capacitor produces no inductive flyback spike, so a diode is pointless; instead the risk is the disc staying charged/biased, so R5 provides a bleed path. Same FET, same gate network — opposite load physics, opposite protection part.

4. Interfaces and pin maps#

• pin 1 BUZZ_ACT — steady-high drive for the active magnetic buzzer BZ1.
• pin 2 BUZZ_PWM — PWM drive for the passive piezo BZ2 (frequency = pitch).
• pins 5/11 GND, pins 6/12 3V3 — doubled power/ground per PMOD Type 1.
• pins 3, 4, 7, 8, 9, 10 — NC on this module.

Both signal pins are inputs to the module (FET gates). There is no open-drain line, no I2C, and nothing the module drives back toward the host.

Internal named nets worth probing on a future PCB:

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

5.1 Connector and shared power#

5.2 Active magnetic buzzer channel (on/off)#

5.3 Passive piezo channel (PWM = pitch)#

Why R5 is a resistor and D1 is a diode — the core teaching point. A diode across BZ1 does real work: an inductor forced to stop conducting develops V = -L·di/dt, a fast spike that D1 catches. A diode across BZ2 would do nothing useful — a capacitor does not generate a flyback spike. What a capacitive disc needs instead is a path to bleed its stored charge so it does not sit at a DC bias between PWM phases; that is exactly what R5's 1 kΩ to 3V3 provides. Matching the protection part to the load's physics is the lesson.

6. Datasheet summary and design interpretation#

Consulted: Alpha & Omega Semiconductor AO3400A, 30 V N-Channel MOSFET, Rev 3.1 (July 2023), <http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf>. The 1N4148WS (Nexperia, SOD-323) is summarized from general knowledge: ~100 V, ~150 mA average forward, fast switching (~4 ns reverse-recovery), Vf roughly 0.7–1 V at these small currents. BZ1 and BZ2 have no datasheet — they are TBD parts; their numbers must be filled in once MPNs are pinned.

No shoot-through is possible. Each channel is a single low-side switch — there is no complementary high-side FET, so there is no half-bridge and no cross-conduction path. The only "both on" concern would be excessive average current if a load shorted, which the FET's 5.7 A rating and the rail limit absorb.

Check the latest datasheet revision and confirm the SOT-23 pinout against the chosen part before procurement.

7. Expected values before bench testing#

Targets assume 3V3 = 3.300 V. BZ1/BZ2 current and SPL are placeholders pending real MPNs. All values are design targets, not measured results.

8. Manual schematic and assembly review checklist#

• Confirm J1 pin 1 orientation: pin 1 = BUZZ_ACT (active), pin 2 = BUZZ_PWM (passive). Swapping them silently swaps the two lessons.
• Verify Q1 and Q2 SOT-23 orientation (gate/source/drain) against the AO3400A footprint; a rotated FET mis-wires the switch.
• D1 polarity is critical: cathode (band) to 3V3, anode to ACT_SW. Reversed D1 is a hard fault (continuous conduction). Confirm during placement.
• Confirm BZ1 is the active part and BZ2 is the passive part, and that BZ1's polarity (if the chosen magnetic buzzer is polarized) matches high-side-to-3V3, low-side-to-ACT_SW.
• Measure R1 = R3 = 1 kΩ (gate series) and R2 = R4 = 10 kΩ (gate pull-down) and R5 = 1 kΩ (piezo bleed) before power.
• Confirm R5 is present and D1 is absent on the piezo channel, and D1 is present and no bleed diode is on the active channel — the two channels are deliberately asymmetric.
• Verify C1 = 100 nF across 3V3/GND, placed close to the two FETs (carry into layout review — layout not yet started).
• Confirm the TBD buzzer MPNs are pinned and their rated current fits the PMOD 3V3 budget before any release build.
• Confirm pins 3,4,7,8,9,10 are NC and not accidentally routed.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, the actual buzzer MPNs fitted (or "TBD prototype part"), measured 3V3, and resistor values. Two contexts are called out throughout:

• Context (a) — PMOD host: plug into a 3.3 V PMOD Type 1 port on the ECP5 host (ULX3S-class). Drive BUZZ_ACT / BUZZ_PWM from FPGA GPIO/PWM.
• Context (b) — standalone 3.3 V bench: wire 3V3/GND from a current-limited bench supply; drive BUZZ_ACT / BUZZ_PWM from a 3.3 V signal source (function generator, Pico, or a manual jumper to 3V3 for the steady-high tests).

A. Unpowered inspection and resistance tests#

1. Complete the §8 checklist under magnification.
2. Measure 3V3-to-GND resistance in both meter polarities; investigate any hard short before applying power.
3. Confirm each gate node reads ~10 kΩ to GND (R2/R4) with the host disconnected, and ~1 kΩ from the gate to its PMOD pin (R1/R3).
4. Confirm R5 reads ~1 kΩ from PZ_SW to 3V3, and that D1 is present on the active channel with correct band orientation.

B. First power, silent-default check#

1. Apply 3V3 with no drive on either line (host tri-stated / jumpers open).
2. Expect no sound from either buzzer and near-zero supply current. Confirm both gate nodes sit at ~0 V — this proves R2/R4 hold the FETs off and the module is silent by default (the correct state for an unconfigured FPGA).
3. Confirm ACT_SW and PZ_SW sit near 3V3 (pulled up through the buzzer / bleed with the FETs off).

C. Active-vs-passive drive verification (the defining test)#

This test proves each channel behaves according to its load type. Do it before anything else acoustic.

1. Steady HIGH on BUZZ_ACT. Drive pin 1 to a static 3.3 V (jumper to 3V3 or set the GPIO high). BZ1 should beep at its fixed pitch — its internal oscillator runs from the DC level. Note: a DC level, not an FPGA tone, produces this sound.
2. Steady HIGH on BUZZ_PWM. Drive pin 2 to a static 3.3 V. BZ2 should be essentially silent — at most a single click as the disc charges. A passive piezo makes no tone from DC.
3. PWM on BUZZ_PWM. Apply a ~4 kHz, ~50% square wave to pin 2. BZ2 should now sing at ~4 kHz. This is the FPGA acting as the oscillator.
4. PWM on BUZZ_ACT (negative test). Applying PWM to pin 1 is wrong/ pointless: the active buzzer just beeps whenever the line is high and chops the beep with the PWM — it does not track the PWM as pitch. Confirm this to internalize the contrast, then stop driving pin 1 with PWM.
5. Record which channel responded to DC and which to PWM. Active = DC/on-off, passive = PWM/pitch. If they are reversed, BZ1 and BZ2 are swapped or the wrong part type was fitted.

D. Flyback capture on the active (magnetic) buzzer#

Purpose: confirm D1 clamps the coil's turn-off spike and understand the Vds margin.

1. Scope the Q1 drain (ACT_SW), GND-referenced, DC-coupled, with enough bandwidth (≥20 MHz) to catch a fast edge. Trigger single-shot on the turn-off edge (BUZZ_ACT high→low).
2. With D1 fitted (normal board): the turn-off overshoot at ACT_SW should be clamped to ≈3V3 + V_f ≈ 4 V and decay quickly. This is the intended behavior.
3. With D1 removed (diagnostic only, brief): the same edge should show a much larger inductive overshoot (V = -L·di/dt), part-dependent, trending toward or beyond the AO3400A's 30 V V_DS(max). An unclamped small-coil spike can approach or exceed the FET rating and repeatedly stress it. Do not run the board this way beyond the measurement.
4. Margin discussion: with D1, ACT_SW peaks ~4 V, leaving ~26 V of the 30 V rating unused — a comfortable margin. Without D1, the margin is uncontrolled and depends on the (TBD) coil. This is the concrete reason the inductive channel gets a diode and the capacitive one does not.
5. Re-fit D1 (band/cathode to 3V3) before continuing.

E. Passive piezo frequency sweep#

1. Drive BUZZ_PWM with a variable square wave and sweep ~200 Hz to ~10 kHz at ~50% duty.
2. Note the frequency where the disc is loudest — expect it near ~4 kHz (mechanical resonance of a 12 mm disc). Measure SPL by ear at a safe distance, or with an SPL meter if available.
3. Scope both the drive at PZ_SW (a clean chopped square wave) and, if you can probe it, the disc voltage, to see the capacitive load's charge/ discharge shape and confirm R5 bleeds it between edges.
4. Duty ≈ loudness: at a fixed frequency, vary duty (e.g. 10% → 50%) and note the loudness change. This is approximate, not a calibrated volume control — record the trend, not an absolute.
5. Confirm the tone stops cleanly when the PWM is removed (R5 discharges the disc; no lingering bias).

F. N-FET gate checks#

1. Off state: with the host tri-stated, confirm both gate nodes measure ~0 V (R2/R4 working → FET off → silent by default). This is the safety-relevant default.
2. On state: drive each line high and confirm the gate reaches ~3.3 V. Compare to the datasheet V_GS(th) (≤1.45 V max): the FET is fully enhanced with R_DS(on) ≈ 22 mΩ (interpolated from the 2.5 V/4.5 V rows).
3. Drop check: with a buzzer conducting, scope the FET low level at ACT_SW/PZ_SW; it should sit only a few mV above GND (R_DS(on) × I), confirming the FET is a good switch, not a linear device.
4. No shoot-through: confirm by inspection there is only one FET per channel (low-side) — there is no high-side device and therefore no cross-conduction path to test for.

G. Host-integration and release tests#

1. In context (a), drive both channels from the eventual HDL (a tone/PWM core for BZ2, a simple gate for BZ1) and confirm clean edges through R1/R3.
2. Verify the chosen buzzers' measured current is within the PMOD 3V3 budget and that C1 keeps the rail quiet when a buzzer switches.
3. Acoustic-emission, EMC, and endurance testing are out of scope for the first article and require pinned MPNs first.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a clean, deliberately asymmetric two-channel switch: two identical AO3400A low-side stages, each with a 1 kΩ gate series resistor and a 10 kΩ pull-down that guarantee silent-by-default behavior for an unconfigured FPGA, differentiated only by their load-appropriate protection — a 1N4148WS flyback diode on the inductive magnetic buzzer and a 1 kΩ bleed resistor on the capacitive piezo. The AO3400A is grossly over-rated for buzzer-level currents (5.7 A, 30 V, ~22 mΩ at the 3.3 V drive), so the FET is never the risk; a 3.3 V gate is ~2× its worst-case threshold and fully enhances it, and the single low-side topology rules out shoot-through. The teaching contrast — steady DC drives the self-oscillating active buzzer, PWM drives the FPGA-is-the-oscillator passive piezo — is the point of the board and the first thing to verify on the bench.

The principal open items are that no PCB exists yet (layout, decoupling placement, and buzzer footprints all unverified), that BZ1 and BZ2 are TBD parts so every current and sound-pressure figure here is a placeholder until real MPNs are pinned and their current is checked against the PMOD budget, that D1 polarity is a load-bearing assembly detail (reversed D1 is a hard fault), and that every expected value in this guide is calculated or reasoned, not measured on hardware. The schematic is ERC-clean (0/0) and the netlist reviewed; nothing here has been fabricated or tested.