Circuit review & bench-test guide

AXO-010 — Dual waveform DAC (MCP4725 I2C + MCP4822 SPI) PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-010-dac, from generate_design.py, the module README.md, and the MCP4725 and MCP4822 datasheets. Never fabricated; values are verification targets.

1. What the board does#

Puts both DAC archetypes on one board: an I2C 12-bit MCP4725 and an SPI dual 12-bit MCP4822 (internal 2.048 V reference, 1×/2× gain). It teaches the DDS/ waveform-generation lesson and contrasts I2C vs SPI on the same job. Outputs go to a header; the PMOD map is hybrid — SPI on pins 1/2/4/7, I2C on 9/10.

PMOD J1  ~CS/MOSI/SCK/~LDAC (1/2/4/7) ─> U2 MCP4822 (SPI)
         SCL/SDA (9/10, JP1/JP2 pull-ups) ─> U1 MCP4725 (I2C)
U1 VOUT, U2 VOUTA/VOUTB ─> 100R ─> J2 output header

2. Safety and scope boundaries#

3.3 V only. PMOD host or 3.3 V bench supply (~50 mA).
DAC outputs are low-current analog — safe, but don't short VOUT to a rail (the 100 Ω series bounds fault current).
Unreleased prototype.

4. Interfaces#

J1 hybrid: SPI 1 ~CS, 2 MOSI, 4 SCK, 7 ~LDAC; I2C 9 SCL, 10 SDA; 5/11 GND, 6/12 3V3. (This dual-bus map is documented in the README — worth re-reading before wiring.)
JP1/JP2 4.7 k I2C pull-ups. JP3 MCP4725 A0 address strap (0x60/0x61).
J2 output header: VOUT(I2C), VOUTA, VOUTB, GND.

5. Component-by-component review#

U1 MCP4725A0 (SOT-23-6, I2C 12-bit): single-channel DAC with EEPROM. Rail-to-rail output referenced to VDD (ratiometric: full-scale = VDD). If absent: no I2C ACK at 0x60/0x61. If VDD is noisy: output noise (it's the reference).
U2 MCP4822 (SOIC-8, SPI dual 12-bit): two channels, internal 2.048 V reference, per-channel 1×/2× gain (so 0–2.048 V or 0–4.096 V, but at 3.3 V supply the 2× range clips above ~3.3 V — documented). ~LDAC transfers the input register to the output. If absent: no SPI output. If ~LDAC handling is wrong: outputs don't update when expected (see below).
~LDAC (pin 7) with pull-down: the board pulls ~LDAC low = transparent latch, so a write takes effect at ~CS rising edge by default. A host that ignores pin 7 still gets output. To do synchronized A+B updates, hold ~LDAC high during both writes then pulse it low. If pulled high with no host drive: outputs freeze (writes never transfer) — the pull-down avoids that.
JP1/JP2 4.7 k pull-ups: I2C bus. If cut with no other pull-ups: no MCP4725 ACK. JP3: MCP4725 address.
100 Ω series on each output: protects the DAC pins from a shorted/miswired load. If absent: a shorted output stresses the DAC.
Decoupling 100 nF (+ bulk): on both parts. MCP4725 especially — VDD is its reference, so ripple = output ripple.

6. Datasheet summary#

MCP4725: VDD 2.7–5.5 V (= reference), I2C to 3.4 MHz, address 0x60–0x67 (A0 strap + fixed bits). Fast-write: 2 bytes (upper/lower 12-bit). Output ratiometric to VDD; settling ~6 µs.
MCP4822: VDD 2.7–5.5 V, SPI mode 0/3 to 20 MHz. 16-bit command: bit15 channel (A/B), bit13 gain (1=1×, 0=2×), bit12 ~SHDN, bits11–0 data. Internal 2.048 V ref. ~LDAC low = immediate transfer on ~CS rising.

7. Expected values before bench testing#

MCP4725 ACK at 0x60 (JP3 default). Write 0x0800 → VOUT ≈ VDD/2 ≈ 1.65 V.
MCP4822 ch A, gain 1×, code 0x800 → VOUTA ≈ 1.024 V; gain 2×, code 0xFFF → clips near 3.3 V (supply-limited, documented).
Outputs settle within microseconds; 100 Ω drop negligible at light load.

8. Manual review checklist#

[ ] Hybrid PMOD map wired correctly (SPI 1/2/4/7, I2C 9/10).
[ ] ~LDAC pulled low (default transparent).
[ ] JP1/JP2 bridged; JP3 address as intended.
[ ] 100 Ω on all three outputs.
[ ] Decoupling close to both parts (MCP4725 VDD especially clean).

9. Ordered bench-test procedure#

A. Unpowered: verify the split PMOD map, ~LDAC pull-down, output series R's, pull-ups; no rail short.

B. Power, idle: 3.3 V. Bus idle-high; both outputs near 0 V.

C. I2C DAC: scan → ACK 0x60. Fast-write 0x0800; measure VOUT ≈ 1.65 V. Sweep 0x000→0xFFF; confirm 0 V→~3.3 V linear ramp (ratiometric to VDD).

D. SPI DAC: write ch A gain-1× code 0x800; measure VOUTA ≈ 1.024 V. Write ch B; confirm independent VOUTB. Try gain-2× and confirm the ~3.3 V clip.

E. ~LDAC sync: hold ~LDAC high, write A and B different codes, confirm outputs unchanged; pulse ~LDAC low, confirm both update together.

F. Waveform: stream a sine table to either DAC; scope the output; confirm DDS-style waveform (MCP4822 audio-rate; note settling limits).

10. Troubleshooting map#

No I2C output: pull-ups cut, wrong address, or ratiometric confusion (VOUT scales with VDD).
SPI output frozen: ~LDAC stuck high (should be pulled low), or wrong SPI mode.
Clipped high on MCP4822 2× gain: expected at 3.3 V supply.

11. Bench record template#

Board: axo-010  I2C ACK: 0x____  VOUT@0x800: __ V
MCP4822 A@0x800(1x): __ V   B independent: [ ]  2x clip observed: [ ]
~LDAC sync update works: [ ]   Sine output clean: [ ]
Notes:

12. Review conclusion#

Two DAC philosophies on one board: ratiometric-to-VDD (MCP4725, so keep VDD clean) vs internal-reference (MCP4822, cleaner but clips at this supply on 2× gain). The ~LDAC pull-down is a deliberate default so naive hosts still see output. Verify each bus independently, then the ~LDAC sync behavior.