← AXO-013

Circuit review & bench-test guide

AXO-013 — analog joystick carrier PMOD module

Document purpose#

This document explains the axo-013-joystick module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and reports/erc.rpt.

This board has never been fabricated or assembled. The schematic is ERC clean (0/0, see reports/erc.rpt) and the netlist has been reviewed, but the PCB layout has not been started — there are no gerbers, no renders, and no physical board. Every number here is a design target or a datasheet expectation to verify, not a proven result. Layout-dependent items (RC/decoupling placement, thumbstick socket clearance from the PMOD clip zone) cannot be reviewed yet and are flagged below.

This is a carrier: it does not contain the joystick. A common 5-pin XY thumbstick breakout (KY-023 class) plugs into socket J2. Because clone breakouts disagree on pin order, Section 4A is a mandatory plug-in-pin-order-verification-before-power gate.

1. What the board does#

AXO-013 digitizes a two-axis analog thumbstick plus its click switch and presents them to a PMOD host over SPI. The stick is mechanically two 10 kΩ potentiometers whose wipers (VRx, VRy) swing rail-to-rail as the stick moves, plus a normally-open switch (SW) that closes to GND when the stick is pressed. A Microchip MCP3202 dual-channel 12-bit SPI SAR ADC digitizes X on CH0 and Y on CH1; the click switch reaches the host as a plain active-low GPIO on PMOD pin 8. Each wiper passes a 1 kΩ + 10 nF RC (fc ≈ 16 kHz) that both filters wiper-scratch noise and acts as the SAR sample-cap charge reservoir.

It teaches SPI ADC transactions, dead-zone/centering math in fabric, and feeds later projects (Pong with the VGA module axo-007, robot teleop with the actuator line). It does not interpret the stick — center offset, dead zone, and axis inversion are all host/HDL responsibilities.

Functional block diagram#

PMOD plug J1 (2x6)
  6/12: 3V3 ──┬────────────┬───────────┬────────────┐
              C4 1uF     C3 100nF    R6 10k       (VDD/VREF U1 pin 8)
              (bulk)     (VDD/VREF)  (~CS PU)
  1: CS_N ───────────────────────────┴──────────────> U1 ~CS (pin 1)
  2: MOSI ──────────────────────────────────────────> U1 DIN (pin 5)
  4: SCK  ──────────────────────────────────────────> U1 CLK (pin 7)
  3: MISO <── R5 100R ── ADC_DOUT ──────────────────── U1 DOUT (pin 6)
  8: JOY_SW <── R4 100R ── SW_RAW ──┬── R3 10k ── 3V3
                                    └────────────────< J2.5 SW (to GND when pressed)

  J2 thumbstick socket (1x5): 1 VCC(3V3) 2 GND 3 VRx 4 VRy 5 SW
    VRx ── R1 1k ──┬── U1 CH0 (pin 2)      C1 10nF ── GND
                   └── JOY_X
    VRy ── R2 1k ──┬── U1 CH1 (pin 3)      C2 10nF ── GND
                   └── JOY_Y
  5/11: GND ──────────────────────────────── U1 VSS (pin 4)

2. Safety and scope boundaries#

• Electrically benign for the operator: single 3.3 V rail, a few mA. Hazards are to the parts. Standard ESD handling.
• Everything on this board is a 3.3 V part. A 5 V PMOD socket or a mis-set bench supply drives VDD/VREF and every ADC input above rating. The MCP3202 absolute-max VDD is 7 V so it tolerates a brief 5 V event better than the ADXL343-class parts, but the stick and the design intent are 3.3 V — verify the rail before every first connection.
• Never back-drive MISO/CS/SCK/MOSI or JOY_SW above VDD+0.3 V, including while the module is unpowered.
• The thumbstick is a mechanical part: do not force it past its stops. Wiper contact bounce/scratch is expected and is what the RC filters and host dead-zone math exist to handle.
• Use a current-limited 3.3 V bench supply (≤50 mA limit is ample) for standalone tests. The whole module should draw well under 1 mA (MCP3202 ~550 µA active typ, plus ~0.66 mA through the two pot end-to-end paths at 10 kΩ across 3.3 V, plus 0.33 mA through R6/R3 pull-ups).
• Center/extents values below are geometry- and part-tolerance-dependent; they are expectations to calibrate, not a specification of this board.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V to PMOD 6/12 and GND to 5/11. C3/C4 charge; U1 VDD/VREF (pin 8) comes up. VREF = VDD is the design intent so the 12-bit code maps linearly to wiper position.
2. R6 (10 kΩ) holds ~CS high while the host FPGA is unconfigured, so U1 stays deselected and no accidental conversion starts on a floating chip-select.
3. The thumbstick's two pots divide 3V3→GND; the wipers sit near mid-rail at physical center and swing toward 3V3 or GND at the extents. R1/C1 and R2/C2 low-pass each wiper (fc ≈ 16 kHz) and present the MCP3202's sample cap a low enough source impedance to settle within the acquisition window.
4. The click switch SW is open at rest; R3 (10 kΩ) holds SW_RAW at 3V3. Press closes SW to GND, pulling SW_RAW low. R4 (100 Ω) series-protects the module-driven JOY_SW line into PMOD pin 8 (active-low).
5. On demand the host asserts ~CS low, clocks a config frame on MOSI to select CH0 (X) or CH1 (Y), and reads the 12-bit result MSB-first on MISO (through R5's 100 Ω). One conversion per axis per transaction.

4. Interfaces#

SPI framing (MCP3202): mode 0,0 or 1,1; ≤ ~0.9 MHz at 3.3 V (the part is 100 ksps class; a 12-bit conversion needs ~18 clocks). ~CS low starts each conversion; the host clocks in a 4-bit config (START=1, SGL/DIFF, ODD/SIGN, MSBF=1), the ADC returns a leading null (0) bit then 12 data bits, and ~CS high ends it. Single-ended CH0 = SGL/DIFF 1, ODD/SIGN 0; CH1 = SGL/DIFF 1, ODD/SIGN 1.

No dedicated test points exist; probe at J1, J2, and the R1–R6/C1–C4 pads. (Layout to-do: add probe-friendly pads before fabrication.)

4A. Plug-in pin-order verification BEFORE power (mandatory carrier gate)#

The thumbstick breakout is not on this BOM and clone pinouts vary. Do this before the breakout is ever plugged into a powered board.

1. Read the breakout's own silkscreen. The J2 map expects, socket pin 1→5: VCC, GND, VRx, VRy, SW. Common clone deviations: VRx/VRy swapped (harmless — just swaps X/Y in software), or GND/VCC swapped or +5V labeled (dangerous — reverses supply into the stick and can feed the wrong rail into the RC nodes).
2. With the breakout unplugged, DMM continuity/ohms across the breakout itself: VCC↔GND should read the two pots roughly in parallel to the wipers (kΩ scale), never a short. VRx and VRy should each read ~5 kΩ to both VCC and GND at mechanical center and sweep as you move the stick. SW should be open to GND at rest and close when pressed.
3. Confirm the breakout is a 3.3 V-tolerant resistive stick (it always is — it is passive), and that it has no onboard regulator or logic that assumes 5 V.
4. Only after the map matches, plug the breakout into J2 with the board unpowered, and re-run Section 9A resistance checks through J2 before applying 3.3 V. A reversed VCC/GND here is the one wiring error that this passive carrier cannot protect against.

5. Component-by-component review#

5.1 ADC and connectors#

5.2 Per-axis RC (anti-alias + SAR source impedance)#

5.3 Button conditioning, SPI support, decoupling#

Power flags #FLG01 (3V3) and #FLG02 (GND) are ERC source markers, not physical parts. Every schematic reference designator (U1, J1, J2, R1–R6, C1–C4) is covered above. There are no jumpers on this module.

6. Datasheet summary and design interpretation#

Primary reference: Microchip MCP3202 datasheet (21034F). Check the revision before procurement.

The thumbstick itself: two ~10 kΩ linear pots and an SPST-NO click switch. Center voltage ≈ VDD/2 only if the pot is mechanically centered and linear; real sticks show a center offset and non-symmetric extents that the host must calibrate.

7. Expected values before bench testing#

None of these have been measured — no board exists.

The canonical first read: MCP3202 CH0 (X) over SPI#

Exact framing (single-ended CH0, MSBF, mode 0,0; the 3-byte host convention):

Assert ~CS low.
MOSI byte 0: 0x01                 (START bit)
MOSI byte 1: 0xA0                 (SGL/DIFF=1, ODD/SIGN=0 -> CH0, MSBF=1)
MOSI byte 2: 0x00                 (clock out the low data bits)
MISO: byte1 lower bits + byte2 = null bit then D11..D0
X code = ((byte1 & 0x0F) << 8 | byte2) masked to 12 bits
Deassert ~CS.  For CH1 (Y) use byte1 = 0xE0 (ODD/SIGN=1).

A first frame that returns 0x000 or 0xFFF stops bring-up: MISO dead (R5 open, DOUT unsoldered), DIN/DOUT swapped, ~CS never asserted, or the part unpowered. A value stuck near mid-scale that never moves with the stick points at a J2 wiring/pot problem, not the ADC.

8. Manual schematic and assembly review checklist#

Reviewable now:

• U1 pin map vs MCP3202 SOIC-8: 1 ~CS, 2 CH0, 3 CH1, 4 VSS, 5 DIN(MOSI), 6 DOUT, 7 CLK(SCK), 8 VDD/VREF. Confirm MOSI→DIN(5) and MISO comes from DOUT(6) through R5 — a DIN/DOUT swap is the classic dead-read cause.
• Confirm CH0 = X (JOY_X) and CH1 = Y (JOY_Y) match the intended axis labels.
• Confirm VREF (pin 8) is tied to 3V3, not left as a separate reference.
• Re-run ERC after any regeneration (reports/erc.rpt clean today).

Assembly items (for the eventual first article — none exists yet):

• J1 pin-1/zigzag vs the PMOD spec and a physical host socket.
• J2 socket orientation and the Section 4A pin-order gate.
• Measure R1–R6, confirm C1/C2 tight to their wiper nodes and C3 tight to U1 pin 8.
• Layout: socket clear of the PMOD clip zone; stick mechanically supported.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, supply voltage, equipment, SPI clock, and operator. Two host contexts: standalone (current-limited bench supply + SPI adapter, phases B–D) and PMOD host (FPGA/MCU provides 3.3 V, phase E). Standalone first. Complete Section 4A before J2 is populated and powered.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification; complete 4A.
2. DMM 3V3-to-GND (J1 pin 6 → 5), both polarities: no hard short.
3. ~CS (pin 1) → 3V3: ≈10 kΩ. JOY_SW (pin 8) → 3V3: ≈10 kΩ (stick released).
4. MISO (pin 3) → U1 DOUT: ≈100 Ω. MOSI/SCK (pins 2/4) → U1 pins 5/7: ≈0 Ω.
5. With the stick fitted: VRx/VRy (J2.3/J2.4) → U1 CH0/CH1: ≈1 kΩ; sweep the stick and watch resistance to 3V3/GND change smoothly.

B. Standalone first power#

1. Bench supply 3.3 V (measure it), current limit 20–50 mA, output off. Wire + to J1 PMOD 6/12, − to 5/11 per the header map.
2. Power on: no current-limit trip; total draw < 1 mA. Milliamps beyond that mean a solder fault or reversed stick supply.
3. Verify 3.3 V at C3/C4/U1 pin 8; ~CS idling at 3.3 V through R6; JOY_SW near 3.3 V; VRx/VRy near mid-rail with the stick centered.

C. Standalone SPI bring-up and axis reads#

Use any 3.3 V SPI master, mode 0,0 (or 1,1), start at ~500 kHz, MSB first.

1. CH0 (X): run the Section 7 frame. Expect a valid 12-bit code near 2048 at center. Capture the first frame regardless of result.
2. CH1 (Y): byte1 = 0xE0. Same expectation.
3. Sweep test: move the stick slowly corner to corner and log both codes. Each axis should move monotonically from near 0 to near 4095; note the center code and the two extents per axis (they are usually asymmetric).
4. Button: read PMOD 8 while pressing the stick — high released, low pressed, clean through R4/R3.

D. Center and extents calibration#

1. Center: stick released, average ≥ 100 samples per axis → X_center, Y_center. Expect ≈2048 ± offset; hundreds of counts offset is normal.
2. Extents: hold each of the four mechanical stops, average → X_min, X_max, Y_min, Y_max. Record all four per axis; they bound the usable range.
3. Dead zone: compute the peak-to-peak jitter at rest (should be a few LSB with the RC filters working); set the host dead zone above it.
4. Repeat after re-centering; center code should return within noise. These numbers are per-stick and per-assembly — this is calibration data, not a pass/fail spec.

E. PMOD-host context (FPGA/MCU provides 3.3 V)#

1. Measure the host socket rail: must be 3.3 V. Confirm the host I/O bank voltage.
2. Plug in with the host unconfigured; verify ~CS reads 3.3 V at the module (R6 vs a floating host pin).
3. Run the same ladder from the host SPI master (bit-banged or the AruviX HDL SPI+MCP3202 core): CH0/CH1 reads, center/extents, JOY_SW GPIO.
4. Scope the first host-driven frame and compare with the phase C capture; confirm the leading null bit and 12 data bits.
5. Demo: dead-zone + centering math in fabric driving Pong (axo-007 VGA) or robot teleop.

F. Release-only tests#

Pot linearity/repeatability characterization, mechanical endurance of the stick, ESD at J1/J2, and temperature behavior belong to a separate qualification plan, gated on a board existing at all.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a clean minimal MCP3202 carrier: both axes digitized ratiometrically (VREF = VDD), 1 kΩ + 10 nF per wiper for scratch filtering and SAR charge, the click switch pulled up and passed out behind 100 Ω, ~CS defended by a 10 kΩ idle pull-up, and DOUT behind the standard 100 Ω line resistor. The principal risks are that nothing physical exists yet (no layout, no first-article data); the passive carrier's inability to protect against a reversed thumbstick VCC/GND, which makes the Section 4A pin-order gate mandatory; SPI framing discipline (leading null bit, correct config bits); and that center/extents are per-stick calibration data, not board specifications. The bring-up ladder — CH0/CH1 12-bit reads, center capture, four-extent sweep, button GPIO — is exactly what the AruviX SPI+MCP3202 HDL core and its dead-zone/centering math will need to reproduce.