Circuit review & bench-test guide

AXO-015 — potentiometer + slider bank PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-015-pots, from generate_design.py, the module README.md, and the MCP3008 datasheet. Never fabricated; values are verification targets.

1. What the board does#

An "analog input fun" board: two rotary pots and one slide pot feed an MCP3008 8-channel 10-bit SPI ADC, giving the host three live analog controls. It's the approachable ratiometric-ADC lesson.

PMOD J1  ~CS/MOSI/MISO/SCK (1/2/3/4) ─> U1 MCP3008 (VREF=VDD=3V3)
2x rotary pot + 1 slide pot wipers ─> RC (1k+10nF) ─> CH0/CH1/CH2
CH3 ─> J3 spare header ; CH4-7 grounded ; MISO via 100R

2. Safety and scope boundaries#

3.3 V only. PMOD host or 3.3 V bench supply (~5 mA).
Pots across 3V3/GND draw a trickle; no hazards.
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 2 SPI: 1 ~CS, 2 MOSI (DIN), 3 MISO (DOUT), 4 SCK, 5/11 GND, 6/12 3V3.
J3 spare CH3 header (bring your own analog signal, 0–3.3 V).

5. Component-by-component review#

U1 MCP3008 (SOIC-16, 8-ch 10-bit SPI ADC): the converter. VREF tied to VDD = 3.3 V, so readings are ratiometric — a pot at mid-travel reads ~512 regardless of small VDD drift (the pot divider and the ADC reference scale together). If absent: no DOUT. If VREF ≠ VDD: readings no longer ratiometric (scale error).
2× rotary pot + 1× slide pot: each wired across 3V3/GND with the wiper to an ADC channel. If a pot's end isn't connected to a rail: that channel reads stuck (0 or full-scale).
RC filter (1 kΩ + 10 nF) per channel: anti-alias / noise filter on each wiper. If absent: noisier codes, especially with a long wire on J3. The 1 kΩ also limits current if a wiper is shorted.
MISO 100 Ω series: protects the ADC-driven DOUT line to the PMOD. If absent: host miswire shorts DOUT.
CH4–CH7 grounded: unused inputs tied to GND (read ~0) rather than floating.
Decoupling 100 nF (+ bulk): on VDD/VREF. If absent: reference noise degrades the low bits.

6. Datasheet summary (MCP3008)#

VDD 2.7–5.5 V; SPI to ~1.35 MHz at 3.3 V (~75 ksps). 10-bit, 8 single-ended or 4 differential.
Transaction: send start bit + SGL/DIFF + 3 channel bits; read back 10 bits MSB-first. Result = 1024 × Vin/VREF.
VREF sets full scale; tying VREF=VDD makes conversions ratiometric to the supply.

7. Expected values before bench testing#

SPI idle: ~CS high. A pot at mid-travel → code ~512; at ends → ~0 and ~1023.
CH4–CH7 → ~0. J3 (CH3) follows whatever 0–3.3 V you apply.
Turning a pot moves its channel smoothly across the range.

8. Manual review checklist#

[ ] VREF tied to VDD (ratiometric).
[ ] Each pot's two ends to 3V3 and GND, wiper to its channel.
[ ] RC (1 k + 10 nF) on each used channel; MISO 100 Ω.
[ ] CH4–7 grounded; decoupling present.

9. Ordered bench-test procedure#

A. Unpowered: verify VREF=VDD, pot end connections, RC filters, MISO series R, grounded spares; no rail short.

B. Power, idle: 3.3 V. ~CS high; MISO idle.

C. ADC alive: read CH4 (grounded) → expect ~0; this confirms the SPI transaction works even before touching a pot.

D. Pot sweep: read CH0/CH1; rotate each pot end-to-end; confirm codes sweep ~0 → ~1023 monotonically. Read the slide pot on CH2; confirm travel maps linearly.

E. Ratiometric check: note a pot's mid code (~512); intentionally drop VDD slightly (still in range) and re-read — the code should barely move (ratiometric), proving VREF=VDD.

F. Spare channel: apply a known DC (e.g. 1.65 V) to J3/CH3 → expect ~512; confirm scale = 1024×Vin/3.3.

10. Troubleshooting map#

Channel stuck at 0/1023: pot end not connected, or wiper open.
All channels wrong scale: VREF not equal to VDD.
Noisy low bits: RC filter missing or decoupling weak.
No DOUT at all: SPI mode/wiring, or ~CS not toggling.

11. Bench record template#

Board: axo-015  CH4(gnd) reads ~0: [ ]
Pot0/Pot1 sweep 0-1023: [ ]  Slide (CH2) linear: [ ]
Mid code: ____  ratiometric (stable vs VDD): [ ]
J3 @1.65V -> ~512: [ ]
Notes:

12. Review conclusion#

A gentle, hazard-free board. The one concept to confirm on the bench is ratiometric behavior (VREF=VDD): a mid-travel pot should read ~512 and stay there as VDD wiggles. Reading a grounded spare channel first is the quickest proof the SPI path works before you touch a control.