Circuit review & bench-test guide

AXO-019 — Memory sampler PMOD module (I2C EEPROM + SPI NOR flash)

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-019-memory, from generate_design.py, the module README.md, and the Microchip 24LC256 and Winbond W25Q128JV datasheets. Never fabricated; values are verification targets.

1. What the board does#

Contrasts the two nonvolatile-memory archetypes on one board: a byte-writable I2C EEPROM (24LC256, 32 KB) and a page/sector NOR flash (W25Q128, 16 MB) on SPI — the same family as the ECP5 boot flash. Hybrid PMOD map: SPI on 1/2/3/4, I2C on 9/10.

PMOD J1  ~CS/MOSI/MISO/SCK (1/2/3/4) ─> U2 W25Q128 (SPI NOR)
         SCL/SDA (9/10, JP1/JP2 pull-ups) ─> U1 24LC256 (I2C EEPROM)

2. Safety and scope boundaries#

3.3 V only (W25Q128JV is a 3.3 V part; 24LC256 spans 1.7–5.5 V). PMOD host or 3.3 V bench supply (~10 mA; flash erase/program spikes higher).
Unreleased prototype.

4. Interfaces#

J1 hybrid: SPI 1 ~CS, 2 MOSI (DI), 3 MISO (DO), 4 SCK; I2C 9 SCL, 10 SDA; 5/11 GND, 6/12 3V3. (Documented in the README — re-read before wiring.)
JP1/JP2 I2C pull-ups. JP3 24LC256 A0 strap (0x50/0x51); A1/A2 tied GND. JP4 24LC256 WP strap. W25Q ~WP/~HOLD pulled up.

5. Component-by-component review#

U1 24LC256 (SOIC-8, I2C EEPROM): 32 KB, byte- and page-writable (64-byte pages). Address 0x50–0x57 via A2:A0. If absent: no I2C ACK. If WP tied high: writes silently fail (reads still work) — the "why won't it write" gotcha.
U2 W25Q128JVS (SOIC-8 208-mil, SPI NOR): 16 MB, 4 KB sector erase, 256- byte page program. If absent: no SPI JEDEC ID. Requires erase-before-write (NOR can only clear bits 1→0 on program; 0→1 needs a sector erase) — the core contrast with the EEPROM.
JP1/JP2 4.7 k pull-ups: I2C bus. JP3 (A0): EEPROM address.
JP4 (WP) on 24LC256: write-protect. Default writable; VDD = protected. If left protected: writes fail.
W25Q ~WP + ~HOLD 10 k pull-ups: must be high for normal operation. If ~HOLD floats/low: the flash pauses/ignores SCK. If ~WP low with SR protection set: status-register writes blocked.
~CS 10 k pull-up (W25Q): keeps the flash deselected until the host drives it. If absent and ~CS floats: spurious selection.
Decoupling 100 nF each: if absent on the flash: erase/program current spikes glitch the bus.

6. Datasheet summary#

24LC256: 1.7–5.5 V, I2C to 400 kHz/1 MHz. Address 0x50 + A2:A0. 64-byte page write (~5 ms internal write cycle — poll for ACK to know completion). 16-bit word address.
W25Q128JV: 2.7–3.6 V, SPI mode 0/3 to 133 MHz. JEDEC ID (0x9F) = 0xEF 0x40 0x18 (Winbond, NOR, 128 Mbit) — the canonical bring-up read. Commands: 0x06 Write-Enable, 0x03 Read, 0x02 Page Program, 0x20 Sector Erase (4 KB), 0x05 Read-Status (bit0 BUSY). Erase/program set the WEL and BUSY bits.

7. Expected values before bench testing#

24LC256 ACK at 0x50 (JP3 default). W25Q JEDEC ID (0x9F) → EF 40 18.
EEPROM: write a byte, poll-for-ACK returns after ~5 ms, read-back matches.
Flash: sector-erase a 4 KB region → reads 0xFF; page-program → reads the written data.

8. Manual review checklist#

[ ] Hybrid map: SPI 1/2/3/4, I2C 9/10.
[ ] JP1/JP2 bridged; JP3 address; JP4 WP default writable.
[ ] W25Q ~WP/~HOLD/~CS pull-ups present.
[ ] Decoupling on both parts.

9. Ordered bench-test procedure#

A. Unpowered: verify the split map, all straps/pull-ups, WP jumper; no rail short.

B. Power, idle: 3.3 V. I2C idle-high; SPI ~CS high.

C. EEPROM alive: I2C scan → ACK 0x50. Read a byte (random-read: dummy write-address then read).

D. EEPROM write: with JP4 = writable, write a known byte at address 0x0000; poll-for-ACK until the ~5 ms cycle completes; read back and compare. Then set JP4 = protected and confirm a write is rejected (read-back unchanged) — the WP lesson.

E. Flash alive: send JEDEC ID (0x9F) → expect EF 40 18. If not, recheck ~CS/~HOLD/~WP pull-ups and SPI mode.

F. Flash erase/program: Write-Enable (0x06), Sector-Erase (0x20) address 0; poll status BUSY until clear; read the sector → all 0xFF. Write-Enable, Page-Program (0x02) 256 bytes; read back and compare. Demonstrate that programming without erasing first can only clear bits (the NOR contrast).

10. Troubleshooting map#

EEPROM reads but won't write: WP tied high (JP4) — the usual cause.
Flash JEDEC ID wrong/00/FF: ~HOLD or ~CS floating, or wrong SPI mode.
Flash program "does nothing": forgot Write-Enable, or didn't erase first.
No I2C ACK: pull-ups cut or wrong address.

11. Bench record template#

Board: axo-019  EEPROM ACK 0x50: [ ]  JEDEC ID: __ __ __ (exp EF 40 18)
EEPROM write/read-back: [ ]  WP blocks write: [ ]
Flash sector-erase->FF: [ ]  page-program read-back: [ ]
Notes:

12. Review conclusion#

The board's teaching content is the erase-before-write contrast: the EEPROM takes arbitrary byte writes (poll-for-ACK), the NOR flash needs Write-Enable + sector-erase then page-program. The two must-verify hardware items are the WP jumper (writes silently fail if protected) and the W25Q ~HOLD/~WP/~CS pull-ups (the flash misbehaves if any float). JEDEC ID EF 40 18 is the flash go/no-go.