← AXS-004

Circuit review & bench-test guide

AXS-004 — Vibration sensor PMOD module

Document purpose#

This document explains the axs-004-vibration PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

This board is a schematic-complete prototype. It has NOT been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. All voltages, time constants, and trip points below are calculated design targets to verify on a first article, not proof that a board works. The SW-420 spring element itself is a generic commodity part with no controlled datasheet (MPN TBD in the schematic) — its behavior is characterized on the bench, not specified.

1. What the board does#

An SW-420 spring-contact vibration element chatters open/closed when shaken. A 1 MΩ pull-up biases its node high; a 10 kΩ / 100 nF RC smooths the chatter into an analog dip; an LMV7219 push-pull comparator slices that dip against a threshold set by a 10 kΩ trimmer (RV1). The host sees clean, fast digital pulses on PMOD Type 1 pin 1 (VIB): the line idles high and pulses LOW while the filtered node is below the trimmer threshold. This is the line's comparator lesson: an analog threshold turns a noisy mechanical contact into countable events, and RV1 makes the threshold-versus-event-rate trade-off tangible.

Functional block diagram#

      3V3 ──┬────────────┬──────────────────┬───────────┐
            │            │                  │           │
           R1 1M        RV1 10k trim       C1 100nF     │
            │            │ (track 3V3→GND)  │ (U1       │
            v            │                 GND  bypass) │
        VIB_ELEM         ├── wiper ── VIB_TH            │
            │            │              │               │
   J2 ── SW-420          │              v               v
   spring element       GND        ┌─ −IN ─────────┐
            │                      │  U1 LMV7219   │── VIB_CMP ── R3 100R ── VIB
           GND        VIB_FILT ────┤ +IN (push-    │              (PMOD pin 1)
            │            ^         │  pull out)    │
            └── R2 10k ──┤         └───────────────┘
                         │
                        C2 100nF
                         │
                        GND

  Idle: element open → VIB_FILT high → +IN > −IN → VIB high.
  Shake: contact chatters → C2 discharges via R2 (τ≈1 ms) → VIB_FILT dips
  below VIB_TH → VIB pulses low; recovers via R1+R2 (τ≈101 ms).

2. Safety and scope boundaries#

• 3.3 V logic only; no hazardous voltages. Risks are to hardware.
• Power only from a Digilent-compatible 3.3 V PMOD host (AruviX ECP5 rev-A or equivalent) or a bench 3.3 V current-limited supply (≤20 mA limit is ample; the module draws ~1.5 mA).
• Do not exceed 3.6 V headroom casually: the LMV7219 absolute maximum supply is 5.5 V (recommended max 5 V), so the comparator tolerates it, but the module is specified as a 3.3 V PMOD device and the trip-point math below assumes 3.3 V exactly.
• Adjust RV1 only with a proper 1.7 mm cross-slot trimmer tool and gentle torque (≤11.76 mN·m per Bourns; pushing force <4.9 N). The TC33X-2 has a rotational STOP — forcing past it breaks the wiper.
• Tap tests mean hitting things: tap the bench beside the board or the board edge with a fingertip or plastic pen, never a metal tool on components, and keep taps away from the (glass-free but open-spring) SW-420 element's solder joints.
• A working bench result is not EMC, ESD, or environmental qualification.

3. Theory of operation and signal sequence#

1. At rest the SW-420's internal spring does not touch its center pin; the element is open. R1 (1 MΩ) pulls VIB_ELEM toward 3.3 V, and C2 charges through R1+R2 so VIB_FILT approaches 3.3 V.
2. Bias-current caveat (calculated, must be verified): the LMV7219's input bias current (450–500 nA typ, 950 nA max at 25 °C, 2 µA max over temperature per the datasheet) flows through R1+R2 ≈ 1.01 MΩ. The idle VIB_FILT therefore sits BELOW 3.3 V by roughly 0.45 V typical — possibly ~1 V at 25 °C worst case and ~2 V at temperature extremes, depending on bias-current direction. The threshold must be set against the MEASURED idle voltage (procedure 9.C), never assumed to be 3.3 V.
3. Vibration makes the spring chatter against the center pin, pulling VIB_ELEM low in sub-millisecond bursts. Each closure discharges C2 through R2 with τ = 10 kΩ × 100 nF = 1.0 ms; dense chatter walks VIB_FILT down.
4. When VIB_FILT crosses below VIB_TH (RV1's wiper voltage), U1's output snaps low in ~10 ns with clean edges guaranteed by ~7 mV of internal hysteresis — no output chatter even on slow crossings.
5. When chatter stops, C2 recharges through R1+R2 with τ ≈ 101 ms, so VIB_FILT climbs back and VIB returns high tens of milliseconds later (e.g., ~70 ms to recross a mid-scale threshold from a full dip). The asymmetric RC (fast fall / slow rise) deliberately stretches events into countable pulses and caps the event rate at a few Hz.
6. The host counts pulses or integrates low-time in fabric to grade shake intensity; turning RV1 changes how deep a dip must be to count.

4. Interfaces#

PMOD Type 1 (GPIO) per Digilent Pmod Interface Specification 1.2.0; pin-1 orientation as verified in ../../pmod-common/PMOD-SPEC-NOTES.md.

VIB is module-driven, idles high, pulses low during vibration.

5. Component-by-component review#

5.1 Sensing element, comparator, threshold#

5.2 Bias, filter, protection, decoupling#

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

All values are calculated design targets on an unbuilt board at 3V3 = 3.30 V.

8. Manual schematic and assembly review checklist#

• Confirm J1 pin-1 orientation against the Pmod-spec recipe before layout sign-off.
• Verify U1 orientation and pin map (1=OUT, 2=V−, 3=+IN, 4=−IN, 5=V+); a swapped input pair inverts the idle polarity — check VIB idles HIGH.
• Confirm RV1 wiring: track ends to 3V3 and GND, wiper (pin 2 of the TC33X pattern) to VIB_TH. A wiper/end swap makes the "threshold" a supply short through 0–10 k — check with an ohmmeter before power.
• Measure R1/R2/R3 (1 M / 10 k / 100 Ω) and confirm C1/C2 placement.
• At layout time: C1 tight to U1; keep the VIB_TH and VIB_FILT nodes short and away from the fast VIB_CMP trace (a 2 ns edge coupling into a 1 MΩ-source-impedance input is a self-oscillation recipe); TI's layout section makes the same points.
• Decide and silkscreen the SW-420 mounting orientation (sensitivity axis).
• Pin the actual SW-420 element source (MPN is TBD in the BOM).
• Mark RV1 on silkscreen as set-and-forget (20-cycle rotational life).
• Confirm silkscreen carries module name, Type 1 badge, pin-1 marker.

9. Ordered bench-test procedure#

Test context: either an AruviX ECP5 rev-A / Digilent-compatible 3.3 V PMOD socket, or a bench 3.3 V current-limited supply (≤20 mA) on pins 6/12 (3V3) and 5/11 (GND), plus a DMM, a two-channel oscilloscope (one channel on VIB_FILT, one on VIB), optionally a logic analyzer for pulse counting, and a 1.7 mm cross-slot trimmer tool. Stop at the first abnormal result; record everything per the template.

A. Unpowered inspection and resistance tests#

1. Visual inspection: U1 orientation, RV1 seated square, R1/R2/R3/C1/C2 values, J2 element joints (element present, not bridged), J1 pin-1 marking.
2. Ohmmeter, board unpowered: 3V3-to-GND should read ≈10 kΩ (RV1 track; ±25%). VIB_ELEM-to-3V3 ≈1 MΩ. VIB_ELEM-to-GND: open at rest; tap the element and watch for momentary continuity (many DMMs are too slow — absence of a beep is not a fail).
3. Rotate RV1 gently end to end (counting against the 20-cycle life — use as few sweeps as possible): wiper-to-GND-end resistance should sweep ~0–10 kΩ smoothly with no dead zones.

B. First power-up, static levels#

1. Apply 3.3 V, current-limited. Expect ~1.2–2.0 mA. Investigate anything above ~5 mA.
2. DMM checks with the board still: VIB_TH equals the wiper setting; VIB_FILT reads the idle level — RECORD IT (this is the bias-droop measurement from section 3.2; compare against the ~2.85 V typ / ≥2.3 V worst-25 °C expectation, or ~3.3 V if bias flows the other way).
3. With VIB_TH set clearly below the measured idle VIB_FILT, VIB must read high (≥3.1 V). Rotate RV1 until VIB_TH exceeds idle VIB_FILT: VIB must snap low. This proves the comparator and establishes the usable threshold band. Return the threshold below idle.

C. Threshold-trimmer setup procedure (the calibration recipe)#

1. Board powered and mechanically still. Clip the DMM between VIB_TH (RV1 wiper) and GND.
2. Measure idle VIB_FILT once more; call it V_idle.
3. Set the trimmer to the expected trip points and verify the divider: full CCW ≈ 0–66 mV, mid ≈ 1.65 V, full CW ≈ 3.23–3.30 V. Deviations beyond the end-resistance allowance indicate a miswired trimmer.
4. For a sensitive setting, set VIB_TH ≈ V_idle − 0.3 V (small dips trip it). For a coarse setting, set VIB_TH ≈ 1.0 V (only deep, sustained chatter trips it). Keep VIB_TH ≤ 2.0 V where possible to stay inside U1's guaranteed common-mode window; if V_idle − 0.3 V is above 2.0 V, note that the sensitive setting operates in the unguaranteed (but functionally expected) region and verify behavior.
5. Record the final wiper voltage. The threshold is now a documented number, not a dial position — taper linearity is unspecified, so the DMM, not the rotation angle, is the calibration.

D. Tap test (comparator output characterization)#

1. Scope CH1 on VIB_FILT (DC, 500 mV/div), CH2 on VIB (or VIB_CMP), timebase 20 ms/div, single-shot trigger on VIB falling.
2. Tap the bench beside the board once, moderately. Expect: VIB_FILT dips with ~1 ms fall segments during chatter, then recovers exponentially (~101 ms τ); VIB drops to ≤0.2 V the instant VIB_FILT crosses VIB_TH and returns high cleanly on the way back — ONE edge each way, no output chatter (that is the 7 mV internal hysteresis at work; propagation delay ~10 ns is invisible at this timebase).
3. Measure and record: dip depth, VIB low-pulse width, recovery time to threshold. Repeat 10 times for statistics.
4. Vary tap strength: light finger tap vs firm knuckle knock. Pulse width and dip depth should grade with energy — this is the raw data for the HDL leaky-integrator exercise.
5. Zoom (10 ns/div class, fast scope, probe on VIB_CMP) on one edge if available: rise/fall in the few-ns range confirms the push-pull stage; check for ringing after R3 on a long PMOD cable — informative for EMC later.

E. Threshold-versus-sensitivity sweep#

1. Fix a repeatable stimulus (e.g., a pen dropped from 5 cm at a marked spot 10 cm from the module).
2. For VIB_TH = 0.5, 1.0, 1.5, 2.0 V and V_idle−0.3 V: run 10 stimuli each; count VIB pulses with the logic analyzer or FPGA counter.
3. Expect a monotonic trend: higher threshold (closer to idle) → more pulses per stimulus; near-zero threshold → few or none. Plot pulses vs threshold; this curve is the module's teaching artifact and the acceptance record for RV1's usable range.
4. At each setting, also confirm zero pulses over 60 s with the bench undisturbed (false-trigger floor). If the floor is nonzero at high sensitivity, suspect building vibration first (move to a padded surface) before blaming the board.

F. Robustness checks#

1. Continuous shake for 30 s: VIB should show a dense but bounded pulse train (recovery τ caps the rate at a few Hz); supply current stays ~2 mA; U1 barely warms (push-pull into 100 Ω + CMOS load is µW).
2. Supply sweep 3.0–3.6 V: verify trip points scale ratiometrically (both VIB_TH and the divider-of-3V3 dip scale together — event behavior should barely change) and record V_idle at each supply.
3. Power-cycle 10 times: VIB must always come up high with the board still (no stuck-low states).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The signal chain is sound and well-matched to its lesson: a gentle 1 MΩ bias on a commodity contact, a deliberate fast-attack/slow-release RC that converts chatter into countable, stretched pulses, and a push-pull hysteretic comparator that guarantees clean edges without an output pull-up. The verified LMV7219 facts (push-pull, 7 mV hysteresis, ns-class edges) confirm the part choice over the open-drain LM393 alternative the README records. The principal findings to resolve or verify at first article are: (1) comparator input bias current through the ~1 MΩ source impedance depresses the idle node by an amount that varies part-to-part and with temperature — the calibration procedure therefore measures V_idle instead of assuming 3.3 V, and a future revision may want R1 = 100 kΩ; (2) the idle node and upper trimmer range sit above the LMV7219's guaranteed common-mode window (VCC−1.2 V ≈ 2.1 V) — expected to work, not guaranteed, so keep working thresholds ≤2 V and verify; (3) the TC33X's 20-cycle rotational life makes RV1 a set-and-forget calibration point, in tension with the "twiddle and observe" teaching use — document it; (4) the SW-420 element has no datasheet, so all sensitivity claims are bench-characterization outputs, not specs; and (5) the board remains a paper design with no layout, fabrication, or first-article evidence.