Circuit review & bench-test guide
AXS-005 — Rotary encoder PMOD module
Document purpose#
This document explains the axs-005-encoder prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.
The board is a schematic-complete prototype only: ERC is clean (0 errors / 0 warnings) and the netlist has been reviewed, but no PCB has been laid out, fabricated, or bench-verified. Every number below is a design target to verify on a first article, not proof that an assembled board works.
1. What the board does#
A 12-pin PMOD Type 1 (GPIO) module carrying an Alps Alpine EC11E15244G1 rotary encoder (30 detents, 15 pulses per revolution) with an integral shaft push switch. Phase A, phase B, and the switch idle high through 10 kΩ pull-ups to the PMOD 3.3 V rail and are pulled to GND as the contacts close. Light 10 nF snubbers take the worst RF edge off the A/B contacts; the real debouncing and quadrature decoding are deliberately left to the FPGA fabric — that is the lesson the module teaches (level L2).
There is no IC on the board. The module draws essentially zero quiescent current; the only current paths are the three pull-ups when contacts close (about 0.33 mA each).
Functional block diagram#
PMOD J1 (Type 1 GPIO) SW1 Alps EC11E15244G1
pin 6/12 3V3 ──┬── R1 10k ── ENC_A_RAW ──── A
├── R2 10k ── ENC_B_RAW ──── B C (common) ── GND
└── R3 10k ── ENC_SW_RAW ─── S1 S2 ────────── GND
│ │ │
C1 10nF ── ENC_A_RAW ── GND │ │ │ (snubbers on A/B only)
C2 10nF ── ENC_B_RAW ── GND │ │ │
│ │ │
pin 1 ENC_A ◄── R4 100R ── ENC_A_RAW
pin 2 ENC_B ◄── R5 100R ── ENC_B_RAW
pin 3 ENC_SW ◄── R6 100R ── ENC_SW_RAW
pin 5/11 GND
2. Safety and scope boundaries#
- This is a 3.3 V logic module. Power it only from a PMOD host socket (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible socket) or from a bench 3.3 V supply with the current limit set low (50 mA is ample).
- Do not plug the module into a host socket that switches its power pins to 5 V. The circuit itself would survive (passives and contacts only), but the host-side assumptions in this guide are 3.3 V LVCMOS.
- The plug is polarized only by convention: pin 1 is the rightmost pin of the upper row viewed from the module top with the connector toward you (Pmod spec 1.2.0 Figure 2, verified in
PMOD-SPEC-NOTES.md). A reversed or offset insertion can put 3.3 V on signal pins. Check orientation before first power; the 100 Ω series resistors limit but do not eliminate miswiring current. - The encoder contacts are rated 10 mA / 5 V DC max and the switch 0.1 A / 5 V DC max. Never wire these contacts to switch anything directly; they are signal contacts only.
- Mechanical: the EC11 shaft takes real hand torque. Until the PCB layout and its mounting are proven, support the board when turning the knob so the plug and solder joints are not the mechanical ground path.
- A working bench result is not a lifetime claim. The encoder is rated 15,000 rotational cycles and the switch 20,000 operations; contact behavior (bounce, chatter, resistance) degrades toward end of life.
3. Signal behavior and design intent#
- At rest, R1–R3 hold ENC_A_RAW, ENC_B_RAW, and ENC_SW_RAW at 3.3 V. The host sees logic high on PMOD pins 1, 2, 3 through R4–R6.
- Rotating the shaft closes/opens the A and B contacts against the grounded common C in quadrature: 15 complete A/B cycles per 360° revolution, with 30 detents — one detent per half cycle.
- Pressing the shaft closes S1 to the grounded S2 and pulls ENC_SW low.
- Falling edges are fast (contact closure to GND). Rising edges are RC: 10 kΩ × 10 nF ≈ 100 µs time constant on A/B. This is deliberately about 20–30x shorter than the specified contact chatter (3 ms max), so it removes RF-fast edges without hiding the bounce the HDL lesson must handle. ENC_SW has no snubber: the push switch bounces hard on purpose.
- Quadrature arithmetic for this exact part: 15 pulses/rev × 4 edges/cycle = 60 quadrature edges per revolution, and 60 / 30 detents = 2 counts per detent in a 4x decoder.
Which phase leads for clockwise rotation is defined by the Alps product drawing. The fetched Alps product page confirms two-phase A/B output but presents the direction diagram graphically, so the CW/CCW lead assignment below is a bench-verification item, not a cited fact: the common EC11 convention is A leads B for clockwise (viewed from the shaft). Capture it and write it down for the HDL driver.
4. External interfaces#
| Reference | Pins/signals | Intended use |
|---|---|---|
| J1 | 12-pin PMOD plug, 2x6, 2.54 mm | Host connection, Pmod Type 1 GPIO |
| PMOD pin | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Net | ENC_A | ENC_B | ENC_SW | NC | GND | 3V3 | NC | NC | NC | NC | GND | 3V3 |
There are no test points on the schematic; probe the resistor pads. The "RAW" side of R4/R5/R6 (encoder side) shows the contact truth; the PMOD side shows what the host sees.
5. Component-by-component review#
5.1 Connector and encoder#
| Ref. | Part / datasheet summary | Function and why needed | If absent/open | If shorted, wrong, or misassembled |
|---|---|---|---|---|
| J1 | 12-pin right-angle PMOD plug | Carries 3V3/GND power in and the three signals out; the only host interface | No power, no signals | Reversed/offset insertion can drive 3.3 V into host pins (limited by R4–R6); a cold joint on pin 5/11 GND floats the entire contact reference |
| SW1 | Alps Alpine EC11E15244G1, 30-detent / 15-pulse encoder with push switch | The sensor itself: A/B quadrature contacts against common C, plus S1/S2 push switch | No function at all | Swapped A/B reverses apparent direction; C not grounded floats both phases high permanently; S2 not grounded makes the switch dead; bent shaft-side pins are a classic hand-solder fault |
Key datasheet parameters for SW1 (from the fetched Alps product page): 30 detents, 15 pulses/rev; detent torque 10 ± 7 mN·m; rotational chattering (bounce during rotation) 3 ms max and switch bounce 2 ms max, specified at R = 5 kΩ; encoder contact rating 10 mA / 5 V DC max with a 1 mA minimum operating current; push-switch rating 0.1 A / 5 V DC with a 500 µA / 5 V minimum; insulation resistance 100 MΩ min at 250 V DC; rotational life 15,000 cycles, switch life 20,000 operations; operating range −40 to +85 °C.
Review finding (accepted, watch on bench): the 10 kΩ pull-ups give only 3.3 V / 10 kΩ ≈ 0.33 mA contact wetting current — below the encoder's 1 mA and the switch's 500 µA stated minimums. This follows the sensor-line standard pull-up value and is common practice for EC11-class parts at logic level, but it is formally out of the minimum-rating box: expect the first symptoms of contact aging (missed or dirty transitions) earlier than the rated life, and treat any flaky-contact bench result as possibly this, not only as dirt.
5.2 Pull-ups, series protection, snubbers#
| Ref. | Value / part | Purpose | What is lost if omitted | Important failure/review point |
|---|---|---|---|---|
| R1 | 10 kΩ (Yageo RC0603FR-0710KL) | Phase A idle-high pull-up; sets contact current and RC rise with C1 | ENC_A floats; host reads noise | Open = floating input; wrong low value raises contact current toward the 10 mA rating and wastes power |
| R2 | 10 kΩ | Phase B pull-up, same role as R1 | ENC_B floats | Same as R1; A/B values must match or edge timing is asymmetric |
| R3 | 10 kΩ | Push-switch pull-up | ENC_SW floats | Same failure modes; no cap on this net, so R3 alone defines the high level |
| R4 | 100 Ω (RC0603FR-07100RL) | Series protection on ENC_A per the line rule (survive host miswiring/contention) | Contention current unlimited into the host pin | Open kills the signal; with a 10 nF snubber downstream-side short the contact discharge current would rise — keep C1 on the RAW side as designed |
| R5 | 100 Ω | Series protection on ENC_B | Same as R4 | Same as R4 |
| R6 | 100 Ω | Series protection on ENC_SW | Same as R4 | Same as R4 |
| C1 | 10 nF 50 V X7R (Murata GRM188R71H103KA01D) | Phase A contact snubber: kills RF-fast contact noise, leaves millisecond bounce for the HDL lesson | Harsher edges, possible EMI/ringing into the host | A short holds ENC_A permanently low; a wrong large value (e.g. 100 nF+) starts genuinely debouncing and defeats the lesson, and slows edges at fast rotation |
| C2 | 10 nF 50 V X7R | Phase B snubber, same role as C1 | Same as C1 | Same as C1; C1/C2 mismatch skews the apparent phase relationship |
| #FLG01, #FLG02 | PWR_FLAG on 3V3 / GND | Schematic-only ERC artifacts marking externally supplied rails | ERC errors | Not physical parts; nothing to assemble |
There is deliberately no decoupling capacitor: the module carries no IC, and the snubbers already provide local charge for contact events.
6. Datasheet summary and design interpretation#
| Device | Key manufacturer facts used here | Board-specific interpretation |
|---|---|---|
| EC11E15244G1 | 30 detents, 15 pulses/rev, 3 ms max rotational chatter, 2 ms max switch bounce (at 5 kΩ), 10 mA/1 mA max/min encoder contact current, 0.1 A/500 µA max/min switch, 15k/20k cycle life | 60 quadrature edges/rev, 2 counts/detent at 4x decode. Bounce budget for the HDL debouncer: design for ≥3 ms, verify measured worst case. 0.33 mA contact current is below the stated minimums — accepted deviation, see 5.1 |
Official reference: EC11E15244G1 product page, Alps Alpine (fetched for this review). The page states output waveform details "vary according to the number of detents and other factors" — pull the full product drawing PDF before release and confirm the phase diagram against the bench capture. Check the exact orderable suffix before procurement.
7. Expected values before bench testing#
| Quantity | Design target / calculated value | What to measure |
|---|---|---|
| Idle level, ENC_A/B/SW | 3.3 V (host rail) | DMM at PMOD pins 1/2/3, contacts open |
| Closed-contact level | ~0 V (contact + trace resistance only; contact R spec 100 mΩ initial) | DMM while holding a detent/press |
| Contact current when closed | ~0.33 mA per closed contact | Infer from rail current or measure across R1–R3 |
| A/B rising-edge time constant | ~100 µs (10 kΩ × 10 nF) | Scope on ENC_A/B rising edge |
| ENC_SW rising edge | Fast (no snubber; host + probe capacitance only) | Scope |
| A/B phase relationship | 90° nominal quadrature; lead swaps with direction | Two-channel scope / logic analyzer |
| Edges per revolution | 60 (15 cycles × 4) | Logic analyzer count over exactly one rev |
| Counts per detent, 4x decode | 2 | Detent-counting test, section 9.D |
| Rotational chatter | ≤ 3 ms per Alps spec (at 5 kΩ; our 10 kΩ may differ) | Scope, single-shot on transitions |
| Switch bounce | ≤ 2 ms per Alps spec (at 5 kΩ) | Scope, single-shot on press and release |
| Module idle current | ~0 (leakage only) | Bench supply current readout |
8. Manual schematic and assembly review checklist#
- Confirm J1 pin-1 orientation against Pmod spec Figure 2 (see
PMOD-SPEC-NOTES.md): odd pins on one row, pin 1 at the correct corner, and 3V3/GND on 6/12 and 5/11 respectively. Buzz plug pins to nets. - Verify SW1 pinout against the Alps drawing: A/C/B on the encoder side (C is the center/common), S1/S2 on the switch side. Confirm C and S2 both buzz to GND.
- Measure R1–R3 = 10 kΩ and R4–R6 = 100 Ω in circuit (expect near-nominal; the network topology does not parallel them significantly).
- Confirm C1/C2 sit on the RAW (encoder) side of R4/R5, and that ENC_SW has no capacitor.
- Inspect SW1 mechanical mounting legs for full solder fill — they are the torque path.
- Confirm no solder bridge between adjacent encoder pins (A–C–B pitch is tight); a C-to-A bridge reads as a permanently low phase.
9. Ordered bench-test procedure#
Stop at the first abnormal result. Record board serial, host or supply identity, equipment IDs, ambient, and operator with every capture.
A. Unpowered inspection and resistance tests#
- Complete the checklist above under magnification.
- Measure 3V3-to-GND resistance at the plug: expect > 100 kΩ (only the pull-up paths through open contacts; essentially open).
- With an ohmmeter from ENC_A (pin 1) to GND, slowly rotate: expect alternating open / ~100 Ω (R4 plus contact) as the A contact closes. Repeat for B (pin 2) and for the switch on pin 3 while pressing.
B. First power and static levels#
- Power from a current-limited bench 3.3 V supply (50 mA limit) via the plug's 3V3/GND pins, or plug into the PMOD host socket unpowered and then power the host.
- Confirm supply current ~0 mA idle, and ~0.33 mA per held-closed contact.
- DMM: pins 1/2/3 read 3.3 V idle; hold the shaft mid-detent / press the switch and confirm ~0 V on the corresponding pin.
C. Quadrature capture (scope / logic analyzer)#
- Probe ENC_A and ENC_B (PMOD pins 1 and 2), GND to pin 5. Scope at ≥1 MS/s or logic analyzer at ≥1 MHz sample rate; bounce hunting later needs single-shot capture.
- Rotate slowly clockwise through several detents. Capture and verify:
- A and B are clean 3.3 V / 0 V levels with the ~100 µs RC rising edge.
- The two channels are in quadrature: each edge of one channel falls near the middle of the other channel's half-cycle (90° nominal).
- Record which channel leads for CW. Repeat counter-clockwise and confirm the lead swaps. This closes the direction-assignment verification item from section 3.
- Rotate through exactly one full revolution (index a knob flat or mark the shaft) and count edges on A+B combined: expect 60. Count full A cycles: expect 15. Count detents by feel: expect 30.
- Spin fast (a few revs/second) and confirm no missed half-cycles and that the RC edges still complete (quarter-period at 3 rev/s ≈ 5.5 ms >> 100 µs).
D. Detent counting / 4x decode test#
- Feed A/B to the FPGA 4x quadrature decoder (or count edges offline from a logic-analyzer trace with 4x decode arithmetic).
- Rotate exactly N = 10 detents CW: expect the 4x count to advance by 2 x N = 20. Rotate 10 detents CCW: expect it to return to the start.
- Repeat 5 times each direction; any drift means missed edges (look for chatter faster than the decoder's synchronizer/debounce) or double counts (decoder bug). Distinguish with the raw capture from step C.
- Verify the rest position: at a detent, A and B should both be in their idle state (typically both high for EC11 15-pulse/30-detent variants — record what this unit does; it constrains the decoder's reset state).
E. Switch verification#
- Scope ENC_SW (pin 3) single-shot, falling-edge trigger. Press the switch ~10 times; capture and measure the worst bounce burst on press and on release. Expect ≤ 2 ms per the Alps spec (specified at 5 kΩ; our 10 kΩ pull-up may lengthen apparent bounce — record actual).
- Confirm clean 3.3 V idle via R3 and ~0 V held-down level, and that the rising edge is fast (no snubber on this net).
- Confirm rotation does not glitch ENC_SW and pressing does not glitch A/B (common-mode mechanical coupling check).
- Feed the measured worst-case bounce into the HDL debouncer parameters: the debounce window must exceed measured bounce with margin, while staying far below the minimum expected press duration.
F. Extended / release-only tests#
Rotational endurance toward the 15k-cycle rating, temperature-range behavior, connector retention force, and knob torque abuse are release-scope tests, not first-bench tests. The 0.33 mA contact-current deviation (5.1) should be revisited if endurance testing shows early contact degradation.
10. Troubleshooting map#
| Symptom | First measurements | Likely areas |
|---|---|---|
| A phase dead (stuck high) | Ohmmeter across the A contact while rotating; R4 continuity | SW1 A pin solder, R4 open, broken contact |
| A or B stuck low | Voltage on RAW node; check C1/C2 for short; solder bridge to C pin | C1/C2 short, A-to-C bridge, crushed contact |
| Both phases dead | Continuity from SW1 pin C to GND | Common pin open — single fault, both phases float or never pull low |
| Direction reads reversed | Compare capture with recorded CW lead | A/B swapped at SW1 or at J1; fix in HDL only with a documented note |
| Count drifts over many detents | Raw single-shot capture at the failing speed | Chatter beyond debounce window; missed edges at fast rotation; decoder synchronizer depth |
| Double counts per detent | Decoder edge arithmetic vs raw trace | 4x decode counting both half-cycles — remember: 2 counts/detent is correct for this part |
| Switch flaky / intermittent | Contact resistance over repeated presses | Contact wetting at 0.33 mA (see 5.1), aging, solder joint |
| Host pin reads mid-level | Voltage both sides of R4–R6 | Series resistor open with host pull-up forming a divider; host pin misconfigured |
| Everything dead | 3.3 V at pins 6/12, GND at 5/11 | Plug orientation, host socket power, harness |
11. Bench record template#
| Field | Record |
|---|---|
| Board revision / serial | |
| Host or bench supply identity, current limit | |
| Scope / logic analyzer, probes, calibration | |
| Ambient conditions | |
| Static levels (idle / closed, all three signals) | |
| CW capture: leading channel, phase sanity | |
| CCW capture: lead swap confirmed | |
| Edges per revolution counted / 60 expected | |
| Detent test: N detents, count delta, drift over 5 runs | |
| Rest-state of A/B at detent | |
| Worst measured A/B chatter (ms) | |
| Worst measured switch bounce, press / release (ms) | |
| Idle and closed-contact supply current | |
| Deviations, raw-file paths, photos | |
| Reviewer / date / disposition |
12. Review conclusion#
The circuit is minimal and coherent: three pulled-up contact signals with series protection, and snubbers scaled (100 µs) to clean RF edges without stealing the debounce lesson from the HDL. The quadrature arithmetic for this exact part (15 pulses, 30 detents, 60 edges/rev, 2 counts/detent at 4x) is fixed by the fetched Alps data and is the core of the bench pass/fail criteria. Open items before release: the CW/CCW lead assignment must be captured and documented (the product page does not state it in text); the 0.33 mA contact current is below Alps' stated 1 mA / 500 µA minimums and is an accepted, documented deviation to watch in endurance testing; and PCB layout, DRC, fab outputs, and the HDL deliverable do not exist yet — nothing in this guide substitutes for first-article measurement.