← AXS-007

Circuit review & bench-test guide

AXS-007 — SHT31 temperature/humidity PMOD module

Document purpose#

This document explains the axs-007-sht31 module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, generate_pcb.py, README.md, and the layout review artifacts in reports/review/.

This board has never been fabricated or assembled. The schematic is ERC clean (0/0) and the PCB layout is routed and DRC clean (0 electrical, 0 unconnected, 0 parity, one waived lib_footprint_mismatch for J1 silk moved to F.Fab), but no physical board exists and there is no first-article bench result of any kind. Every number in this guide is a design target or a datasheet expectation to verify, not a proven result.

1. What the board does#

AXS-007 is a PMOD Type 6 (extended) I2C peripheral carrying a Sensirion SHT31-DIS-B digital temperature and relative-humidity sensor. The host FPGA or MCU supplies 3.3 V through the PMOD plug and talks I2C at address 0x44 (default) or 0x45 (JP3 restrapped). On-board 4.7 kΩ pull-ups on SCL/SDA can be disconnected by cutting solder jumpers JP1/JP2 when the module is chained behind another module that already provides pull-ups. The sensor's ALERT output and active-low reset are brought to PMOD pins 1 and 2; the I2C bus is repeated on the bottom row (pins 9/10) for daisy-chain experiments.

It contains no regulator, no level shifting, and no protection beyond a 100 Ω series resistor on the sensor-driven ALERT line. It is a 3.3 V-only module; the host defines the rail.

Functional block diagram#

PMOD plug J1 (2x6, right-angle)
  6/12: 3V3 ────┬──────────────┬───────────────────┐
                │              │                   │
              C2 1uF        C1 100nF          R1/R2 4.7k     R3 10k
              (bulk)        (at U1 VDD)       (pull-ups)     (pull-up)
                                               │    │           │
  3: SCL ──────────────────────────────┬── JP2 ┘    │           │
  4: SDA ──────────────────────────┬───│── JP1 ─────┘           │
  9: SCL (chain) ──────────────────│───┤                        │
 10: SDA (chain) ──────────────────┤   │                        │
                                   v   v                        │
  2: ~RESET ──────────────────> U1 SHT31-DIS-B <── RESET_N ─────┘
                                   │        ADDR <── JP3 (1-2 GND = 0x44,
  1: ALERT <───── R4 100R ── SHT_ALERT            2-3 3V3 = 0x45)
  5/11: GND ── GND pours both layers ── U1 VSS, pin 7 (R), die pad

2. Safety and scope boundaries#

• Voltages are low (3.3 V) and currents are microamps; the main hazards are to the board, not the operator. Standard ESD handling applies — the sensor is rated 4 kV HBM but the exposed PMOD pins connect straight to U1.
• 3.3 V only in this design. The SHT31 itself tolerates 2.15–5.5 V, but the AruviX module rules and the PMOD spec fix the rail at 3.3 V; do not plug into a 5 V host.
• Use a current-limited bench supply (≤50 mA limit is ample) for standalone tests. The whole module should draw microamps at idle.
• The SHT31 is a calibrated hygrometer. Do not touch the sensor opening, do not clean the assembled board with solvents near U1, and follow Sensirion's handling instructions for soldering and storage. Long exposure outside 5–60 °C / 20–80 %RH can temporarily offset the RH reading.
• Do not apply voltage to SDA/SCL/ALERT/~RESET above VDD+0.3 V (absolute maximum per pin), including when the module is unpowered.
• A working I2C conversation is not a calibration claim. Accuracy statements (±0.2 °C, ±2 %RH) are Sensirion's, valid only for an undamaged, correctly reflowed sensor; verify against a reference if accuracy matters.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V to pins 6/12 with GND on 5/11. C2 (1 µF) and C1 (100 nF) charge; there is no inrush concern.
2. U1 powers up once VDD crosses V_POR (1.8–2.15 V). Sensirion specifies a maximum VDD slew of 20 V/ms — a bench supply or PMOD hot-plug is fine; an extremely fast solid-state switch could in principle violate this.
3. After t_PU (0.5 ms typical, 1 ms max), U1 is in idle state and accepts commands. R3 (10 kΩ) holds ~RESET high so an unconfigured FPGA pin cannot float the sensor into reset; U1 also has an internal ~50 kΩ pull-up on nRESET.
4. JP3 straps ADDR: default bridge 1-2 ties ADDR to GND → I2C address 0x44; bridge 2-3 instead ties ADDR to 3V3 → 0x45. ADDR must never float.
5. SCL/SDA idle high through R1/R2 (4.7 kΩ, via JP1/JP2). The host issues I2C commands; U1 is a slave only.
6. On alert conditions (programmable RH/T limits), U1 drives ALERT high; the signal reaches PMOD pin 1 through R4 (100 Ω series, sensor-driven-line miswire-tolerance rule).

4. Interfaces#

Note the 2×6 header zigzag-vs-PMOD-row numbering translation: on the physical J1 header, PMOD pins 1–6 map to odd header pads 1/3/5/7/9/11 and PMOD 7–12 to even pads 2/4/6/8/10/12 (see PMOD_TO_HEADER in the common library and the pcb.connect table in generate_pcb.py). Buzz this out before first power.

There are no test points; probe the J1 pins, the jumper pads, and the passive pads directly.

5. Component-by-component review#

5.1 Sensor and connector#

5.2 Decoupling#

5.3 Pull-ups, series protection, and straps#

Every reference designator on the board is listed above (U1, J1, C1, C2, R1–R4, JP1–JP3). There are no other components.

6. Datasheet summary and design interpretation#

Primary reference: Sensirion SHT3x-DIS datasheet, Version 7, December 2022 (also linked from the SHT31 product page). Check for a newer revision before procurement.

7. Expected values before bench testing#

None of these have ever been measured on this design — no board exists.

CRC-8 worked example#

Polynomial 0x31, init 0xFF, MSB-first, no reflection, no final XOR. Over the datasheet example word 0xBE 0xEF the result is 0x92 (datasheet Table 20). For a temperature word of exactly 25.00 °C, S_T = 0x6666:

crc = 0xFF
crc ^= 0x66            -> 0x99
8x: shift left, XOR 0x31 when the bit shifted out was 1   -> 0xF1
crc ^= 0x66            -> 0x97
8x: same rule                                             -> 0x93

So the frame 0x66 0x66 0x93 is self-consistent. Similarly 0x7F 0xFF 0x8F is a valid 50.0 %RH humidity word. Conversions:

• T = −45 + 175 × 26214 / 65535 = 25.00 °C
• RH = 100 × 32767 / 65535 = 50.0 %RH

Use these vectors to check the host-side CRC and conversion code before ever touching hardware.

8. Manual schematic and assembly review checklist#

Layout evidence to inspect (no fabricated board exists; this is the routed design): reports/review/ contains axs-007-layout-review.html (the layout review report), top.svg and bottom.svg (copper/silk plots), and raytraced renders render-top.png/.jpg, render-bottom.png/.jpg, render-iso.png/.jpg. Open the HTML report and both SVGs and verify the points below.

• U1 is placed at the top edge, deliberately away from the connector. Thermal isolation is by distance only — there is no milled slot or copper keepout around the sensor in this revision, and both layers carry full GND pours that thermally couple U1 to the rest of the board. For a breadboard-class module this is acceptable; note it as a known limitation when judging absolute temperature accuracy (self-heating from the host through the pours, and Sensirion's design guide recommends slotting for precision applications).
• Verify J1 pin-1 position against the Digilent PMOD spec 1.2.0 Figure 2 (pin 1 top-right, pins 1–6 upper row) and against a physical host socket; the README flags the host-socket cross-check as still open (ECP5 rev-A review item).
• Buzz the header zigzag mapping: PMOD pin 3 (SCL) = header pad 5, PMOD pin 4 (SDA) = header pad 7, etc., per generate_pcb.py.
• Confirm U1 orientation (DFN pin 1 dot), that pin 7 (R) and the die pad are tied to GND, and that the exposed pad is actually soldered (X-ray or edge inspection on the eventual assembly).
• Confirm JP3 is bridged 1-2 (and only 1-2), JP1/JP2 bridged.
• Measure R1–R4 values on the assembled board before first power if any hand-rework happened.
• Check C1 sits adjacent to U1 VDD (it is at x=104.4 next to the sensor in the layout) and that the GND stitching vias next to U1/C1/C2 exist.
• Silkscreen sanity: front "AXS-007 SHT31 T/RH" and "PIN1" marker; back rev and pin-map legend ("1:AL 2:RS 3:SCL / 4:SDA I2C 0x44").

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, jumper states, equipment, ambient T/RH, and operator for every phase. Two host contexts are covered: standalone (current-limited bench supply, phases B–C) and PMOD host (FPGA/MCU providing 3.3 V, phase D). Do standalone first — it risks only the module.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. DMM 3V3-to-GND at J1 pins 6→5, both polarities: no hard short.
3. SDA→3V3 and SCL→3V3: ≈4.7 kΩ each. Cut-test rehearsal: this is also the jumper verification you will repeat whenever JP1/JP2 change state.
4. ~RESET→3V3: ≈10 kΩ (R3; the sensor's internal 50 kΩ is not visible unpowered). ALERT→any rail: open (only R4 in series to U1's pin).
5. JP3 center→GND: ≈0 Ω (default strap). JP3 center→3V3: open.

B. Standalone first power (current-limited bench supply)#

1. Bench supply 3.3 V, current limit 20–50 mA, output off. Wire supply + to J1 PMOD pin 6 (or 12) and − to pin 5 (or 11). Double-check against the zigzag mapping — on the physical header these are pads 11 and 9.
2. Power on. Expect no current-limit trip and, on a µA meter, an idle draw of a few µA once C1/C2 are charged. Tens of mA means a short or reversed connection: power off and investigate.
3. Verify 3.3 V at U1's C1 pads, SCL/SDA idle at 3.3 V, ~RESET at 3.3 V, ADDR at 0 V.
4. Momentarily short ~RESET (J1 pin 2) to GND (≥1 µs is enough) and release; supply current should stay in the µA range afterwards.

C. Standalone I2C bring-up (bus adapter, still on bench supply)#

Use any 3.3 V I2C master (FT232H/Bus Pirate/MCU devboard). Common ground with the bench supply; master pull-ups off first, since the module provides them.

1. Pull-up source check: with the adapter attached and idle, SCL/SDA must read 3.3 V. Cut nothing yet. (If this module will later be chained, re-run this step after cutting JP1/JP2: the bus must still idle high — now through the host/other-module pull-ups — and an adapter with its pull-ups disabled must see the lines float, proving the cut is real.)
2. Address scan: expect an ACK at 0x44 only. No ACK anywhere: check SDA/SCL swap, U1 soldering. ACK at 0x45: JP3 is strapped high or floating. ACK at both: two devices or a scan artifact — capture the waveform.
3. Restrap check (once per design validation, not per board): move JP3 to 2-3, rescan: ACK at 0x45 only. Restore 1-2.
4. Soft reset: write command 0x30A2 (bytes: address+W, 0x30, 0xA2, all ACKed). Wait ≥1.5 ms.
5. Status register: write 0xF32D, read 3 bytes: expect 0x80 0x10 + valid CRC (0x8010 = alert-pending and reset-detected set after reset). Send clear-status 0x3041, re-read: bits 15/4 now clear.
6. First measurement: write 0x2400 (single shot, high repeatability, clock stretching disabled). Because stretching is off, a read header issued too early is NACKed — verify that behavior once, deliberately. After ≥15 ms, read 6 bytes: T MSB, T LSB, CRC, RH MSB, RH LSB, CRC.
7. CRC check: run both words through the section 7 CRC-8 (poly 0x31, init 0xFF). Both must match. Convert: T = −45 + 175·S_T/65535, RH = 100·S_RH/65535. Expect ambient within a couple of °C/%RH of a reference thermometer/hygrometer.
8. Clock-stretching variant (optional): issue 0x2C06 and confirm the sensor stretches SCL until data is ready — useful later as an HDL corner case.
9. Plausibility stimulus: breathe gently near (not on) the sensor: RH rises sharply, T slightly; both recover. This is a function check, not calibration.
10. ALERT sanity (optional): program alert limits per Sensirion's alert application note, or at minimum confirm ALERT (J1 pin 1) is driven (not floating) and status bit 15 tracks it.

D. PMOD-host context (FPGA/MCU provides 3.3 V)#

1. Verify the host PMOD socket really supplies 3.3 V (measure it) and that the host I/O bank is 3.3 V. Power the host, then plug the module in with host power off if hot-plug policy is unclear.
2. With host I/O still unconfigured, measure SCL/SDA/~RESET on the module: all must idle at 3.3 V (R1/R2/R3 doing their job against floating host pins — this is exactly why R3 exists).
3. Run the same sequence as phase C from the host (software I2C or the AruviX HDL I2C master when it exists): scan → 0x44 ACK, soft reset, status, 0x2400, CRC-checked conversion.
4. If the host provides its own pull-ups (many FPGA boards do not; some MCU pins do), decide the pull-up ownership: for a single module keep JP1/JP2 bridged and host pull-ups off. Measure the SCL/SDA low level: ≤0.4 V.
5. Daisy-chain experiment (design intent of pins 9/10): connect a second I2C device or module to the bottom-row bus. Exactly one set of pull-ups should remain; cut JP1/JP2 on the downstream module and re-verify idle levels and V_OL.
6. Soak: log one measurement per second for 30+ minutes. Zero CRC failures and zero NACKs expected; log T/RH drift (sensor self-heating at 1 mps, lowest repeatability, is negligible per the datasheet average-current figures; high-rate periodic modes can self-heat).

E. Release-only tests#

Accuracy verification against a calibrated reference (or saturated-salt humidity fixtures), reflow-profile qualification of the sensor, long-term drift, and ESD are out of scope for the first bench pass and must be planned separately before any release claim.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is a minimal, coherent implementation of Sensirion's application circuit plus AruviX line rules: mandatory 100 nF at VDD, bulk at the plug, jumpered pull-ups for chain topology, a defensive ~RESET pull-up, a series resistor on the one sensor-driven line, and a proper two-state ADDR strap. The routed PCB is DRC clean and the renders/report in reports/review/ allow a full desk review. The principal risks are unverified first-article behavior (nothing has ever been built), the J1 pin-1/zigzag orientation against a real host socket, DFN/exposed-pad solderability, thermal coupling through the unslotted GND pours limiting absolute temperature accuracy, and pull-up ownership mistakes in chained configurations. The I2C bring-up sequence in section 9 — scan, soft reset 0x30A2, status 0xF32D, measure 0x2400, CRC-8 verify, convert — is deliberately the same sequence the AruviX Verilog I2C master will have to reproduce.