← AXS-008

Circuit review & bench-test guide

AXS-008 — BMP280 barometric-pressure PMOD module

Document purpose#

This document explains the axs-008-bmp280 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the Bosch BMP280 datasheet.

The board is a schematic-only prototype: ERC is clean (0/0), but no PCB has been laid out and no board has ever been fabricated or powered. There are no recorded bench results of any kind. Every numeric value in this guide — voltages, currents, register contents, timings, compensation results — is a verification target taken from the schematic and the manufacturer datasheet, not a measured result. Do not treat anything below as proof that an assembled board works or is safe.

1. What the board does#

The board puts a Bosch BMP280 absolute barometric-pressure and temperature sensor on the AruviX PMOD template (Type 6 extended, I2C). The PMOD host supplies the single 3.3 V rail. CSB is hard-wired to 3V3 so the part latches into I2C mode from power-on; SDO is the I2C address bit and is driven by solder jumper JP3 (default 1-2 = GND = address 0x76; 2-3 = 3V3 = 0x77). The 4.7 kΩ bus pull-ups R1/R2 connect to the bus through solder jumpers JP1/JP2 (bridged by default) so they can be removed when another chained module provides the pull-ups. Pins 9/10 repeat SCL/SDA for daisy-chaining. The BMP280 has no interrupt pin, so PMOD pins 1/2/7/8 are NC.

The lesson content is the I2C master FSM plus the BMP280's burst register reads, one-time calibration-block readout, and 32/64-bit fixed-point compensation arithmetic.

Functional block diagram#

PMOD host (3.3 V)                 axs-008-bmp280
┌──────────────┐      J1
│ 3V3 ─────────┼── 6/12 ──┬───────────────┬───────────────┐
│ GND ─────────┼── 5/11 ──┼───────┐       │               │
│              │          │       │      C1,C2         JP3 2-3 (0x77)
│ SCL ─────────┼── 3/9 ───┼──┬────┼──── U1 BMP280         │
│ SDA ─────────┼── 4/10 ──┼──┼─┬──┼──── (CSB=3V3, I2C)    │
└──────────────┘          │  │ │  │       │ SDO ── JP3 ── GND (1-2, 0x76)
                          │  │ │  GND
              R2 4.7k ── JP2 │ │
              (3V3→SCL_PU)   │ R1 4.7k ── JP1
                             │ (3V3→SDA_PU)
                             └── bus repeated on J1 pins 9/10 for chaining

2. Safety and scope boundaries#

• This is a 3.3 V logic-only module. Power it only from a PMOD host or a current-limited bench supply set to 3.30 V. The BMP280 absolute maximum on any supply pin is 4.25 V and on any interface pin VDDIO + 0.3 V; there is no on-board protection, regulator, or reverse-polarity guard.
• Set the bench-supply current limit low (≈20 mA) for first power-on. The sensor itself should draw microamps; anything near the limit indicates a fault.
• The LGA-8 metal-lid package is moisture/ESD sensitive (HBM ±2 kV). Use ESD precautions; do not probe the LGA pads with sharp tips harder than needed.
• Do not blow compressed air, solvents, or conformal coating into the sensor vent hole; do not exceed the 0–20000 hPa absolute-maximum pressure.
• A working I2C conversation is not a calibration statement. Accuracy claims (±1 hPa absolute, ±0.12 hPa relative) are datasheet figures for correctly reflowed production parts, and this prototype has never been through assembly or bench verification.

3. Power and control sequence#

1. The PMOD host (or bench supply) applies 3V3 and GND on J1 pins 6/12 and 5/11. Both VDD and VDDIO of U1 are on this single rail; C1/C2 provide local decoupling. #FLG01/#FLG02 are ERC-only power-flag artifacts marking the host as the rail source — they place no physical part.
2. CSB is tied to 3V3, so at power-on-reset the part selects I2C mode and (per datasheet section 5.1) cannot fall into SPI mode from a bus glitch. SDO is held at GND (JP3 1-2 default) → address 0x76.
3. Datasheet start-up time is ≤2 ms to first communication (after VDD > 1.58 V and VDDIO > 0.65 V). During POR the NVM calibration words are copied to the register image (status 0xF3 bit 0 im_update).
4. The device wakes in sleep mode (mode[1:0] = 00, ctrl_meas 0xF4 = 0x00); sleep current is 0.1 µA typical. The bus idles with SDA and SCL pulled to 3.3 V through R1/JP1 and R2/JP2.
5. The host configures oversampling and mode via 0xF4 (and optionally 0xF5), polls status 0xF3 or waits out the measurement time, then burst-reads 0xF7–0xFC and applies the calibration compensation math.

4. Interfaces: PMOD pin map, jumpers, test points#

PMOD plug J1 (Type 6 extended)#

Solder jumpers#

Test points#

There are no dedicated test points on this design. Probe at the J1 pins, the jumper pads (JP1/JP2 for the bus, JP3 centre pad for SDO), and the C1/C2 pads for the rail. Add test points at PCB layout time if bench work shows they are needed.

5. Component-by-component review#

Every reference designator in generate_design.py is covered.

6. Datasheet summary and design interpretation#

Official references: BMP280 datasheet (BST-BMP280-DS001) and the Bosch Sensortec BMP280 product page. Check the latest datasheet revision before procurement.

7. Expected values before bench testing#

All of these are design targets, not measurements.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation against the clockwise-numbered LGA-8 footprint (Bosch_LGA-8_2x2.5mm_P0.65mm_ClockwisePinNumbering); pin 1 marking on silk must match the package dot. A rotated LGA is the most likely destructive assembly error on this board.
• Verify the netlist mapping recorded in generate_design.py: pin 2 CSB → 3V3, pin 3 SDI → SDA, pin 4 SCK → SCL, pin 5 SDO → JP3 common, pins 6/8 VDDIO/VDD → 3V3, pins 1/7 → GND.
• Confirm JP3 is bridged 1-2 only, and JP1/JP2 are bridged, before power.
• Buzz J1: pins 5/11 to GND, 6/12 to 3V3, 3–9 and 4–10 continuity (chained bus), pins 1/2/7/8 isolated.
• Measure 3V3-to-GND resistance in both meter polarities; investigate any hard short before power (suspect C1/C2 or a JP3 double bridge).
• Check that no solder has wicked into the U1 vent-hole area and that flux was not trapped under the metal lid.
• Confirm the PCB (once laid out) keeps the vent hole exposed and puts C1/C2 within a few millimetres of U1's supply pins. This review item cannot be closed until layout exists.

9. Ordered bench-test procedure#

Assumed setup: a PMOD host FPGA board or a current-limited 3.3 V bench supply wired to J1 pins 6/12 (3V3) and 5/11 (GND), plus any I2C master (FPGA core under test, USB-I2C adapter, or MCU dev board) on pins 3/4. Stop at the first abnormal result and record everything with board serial, equipment IDs, and ambient conditions.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Meter, unpowered: 3V3-to-GND in both polarities — no hard short.
3. SDA-to-3V3 ≈ 4.7 kΩ, SCL-to-3V3 ≈ 4.7 kΩ (through R1/JP1 and R2/JP2).
4. JP3 common (U1 SDO) to GND ≈ 0 Ω; JP3 common to 3V3 open.
5. SDA-to-SCL: open (no bridge between bus lines).

B. First power-on#

1. Bench supply 3.30 V, current limit ~20 mA. Power the board with no I2C master attached.
2. Supply current: expect the meter floor (sub-µA device draw). More than ~1 mA means a short or damaged part — power off and investigate.
3. Probe SDA and SCL: both at 3.3 V (bus idle high through the pull-ups).
4. Probe JP3 common: 0 V (SDO low, address 0x76).

C. Bus idle and address-ACK scan#

1. Attach the I2C master (100 kHz for bring-up). Confirm idle levels remain 3.3 V on both lines.
2. Run a full 7-bit address scan (0x08–0x77). Expected: exactly one ACK, at 0x76 (write byte on the wire: 0xEC).
3. Move JP3 to 2-3 (or hold the SDO pad high through a 10 kΩ test resistor) and rescan: exactly one ACK at 0x77 (wire byte 0xEE). The datasheet allows the address to change live — no power cycle needed — but restore JP3 to 1-2 afterwards and rescan to confirm 0x76.
4. Any extra ACKs mean a solder bridge on SDA/SCL or a misbehaving master.

D. Chip-ID read and soft reset#

1. Read register 0xD0. On the wire: S 0xEC A 0xD0 A Sr 0xED A 0x58 N P. Expected data byte 0x58 exactly. (Bosch samples returned 0x56/0x57; mass-production BMP280 is 0x58 — a BME280 fitted by mistake returns 0x60.)
2. Write 0xB6 to 0xE0 (soft reset), wait ≥2 ms, re-read 0xD0 → 0x58 again; read 0xF4 → 0x00 (sleep mode after POR); read 0xF7 → 0x80 and 0xFA → 0x80 (data registers at reset state, no measurement yet).

E. Calibration-block burst read and plausibility check#

1. Burst-read 24 bytes starting at 0x88 (auto-increment): S 0xEC A 0x88 A Sr 0xED A d0…d23 N P. These are dig_T1…dig_P9, LSB first per word (0x88/0x89 = dig_T1 low/high … 0x9E/0x9F = dig_P9; 0xA0/0xA1 are reserved).
2. Reject a read of all 0x00 or all 0xFF — that indicates a bus or NVM problem, not real trim data.
3. Plausibility bounds (each production part differs; the datasheet worked example is dig_T1=27504, dig_T2=26435, dig_T3=−1000, dig_P1=36477, dig_P2=−10685, dig_P3=3024, dig_P4=2855, dig_P5=140, dig_P6=−7, dig_P7=15500, dig_P8=−14600, dig_P9=6000):

• dig_T1, dig_P1 (unsigned) in the tens of thousands, neither 0 nor 65535;
• dig_T2 positive and of order 20000–30000;
• the signed words within roughly ±3× the example magnitudes.

1. Re-read the block twice; both reads must be identical (NVM is static).

F. First measurement and compensation-math sanity check#

1. Write ctrl_meas 0xF4 = 0x27 (osrs_t=×1, osrs_p=×1, mode=normal) and config 0xF5 = 0x00 (filter off, minimum standby). Alternatively use forced mode 0xF4 = 0x25 per conversion.
2. Poll status 0xF3 until bit 3 (measuring) is 0, or wait ~10 ms (exact max conversion time at ×1/×1 oversampling: verify against datasheet chapter 3.8 — this guide did not extract Table 13).
3. Burst-read 6 bytes from 0xF7: press_msb/lsb/xlsb, temp_msb/lsb/xlsb. Assemble the 20-bit raw values: adc = (msb<<12) | (lsb<<4) | (xlsb>>4). Neither may still be 0x80000 (the "skipped" marker) or stuck at the 0x80/0x00/0x00 reset pattern.
4. Run the datasheet compensation code (§3.11.3/§8) with the calibration words from step E. Cross-check the implementation first with the datasheet worked example: adc_T=519888, adc_P=415148 with the example trim set must produce T = 25.08 °C (t_fine=128422) and P = 100653.27 Pa. If your fixed-point pipeline reproduces those numbers, it is correct.
5. Plausibility of the live reading: temperature ~15–35 °C on an indoor bench (expect it slightly above room ambient from self-heating); pressure ~950–1050 hPa at typical altitudes (at ~1500 m elevation expect ~850 hPa — adjust the bound to the lab's altitude).
6. Stimulus checks: rest a fingertip near (not on) the vent — temperature must rise over tens of seconds. Move the board vertically by ~1 m or gently press the module in a small closed box — pressure must respond in the expected direction (~0.12 hPa per metre of altitude).

G. JP1/JP2 pull-up jumper verification (chaining)#

1. Unpowered, JP1/JP2 bridged (default): ohmmeter SDA-to-3V3 ≈ 4.7 kΩ, SCL-to-3V3 ≈ 4.7 kΩ.
2. Cut JP1 and JP2 (knife through the bridge, verify under magnification): SDA-to-3V3 and SCL-to-3V3 now read open (>1 MΩ; a slow-settling reading through the meter is the U1 pad ESD structure, not a resistor).
3. Powered with pull-ups cut and no external pull-ups: the bus floats — confirm the scan now fails (this is the expected failure signature of a chained module whose partner is missing).
4. Add external 4.7 kΩ pull-ups (or a partner module with its jumpers bridged) and re-run sections C–F: identical results expected.
5. To restore single-module operation, re-bridge JP1/JP2 with solder and re-verify step 1.

H. Multi-module chain (optional, needs a second I2C PMOD)#

1. Chain a second module on pins 9/10. Exactly one module in the chain may keep JP1/JP2 bridged.
2. If the second device is another BMP280/BME280 board, set its JP3 to 2-3 so the addresses are 0x76 and 0x77; scan must show both, and chip-ID reads must return 0x58/0x60 respectively.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a minimal, coherent I2C sensor module: single-rail BMP280 with both supplies decoupled, CSB hard-tied high so the interface mode can never be glitched into SPI, SDO firmly defined by JP3 (never floating), and removable pull-ups for chained operation. The design intentionally has no level shifting, protection, or regulation — the PMOD host owns the rail, and that boundary must be respected on the bench.

Principal open risks: the board exists only as a schematic (no layout, no DRC, no fab outputs); the LGA-8 orientation and vent-hole handling are assembly risks that cannot be reviewed until layout; there is no bench evidence for any number in this guide; and the compensation-math pipeline in fabric is unwritten — validate it against the datasheet worked example before trusting any live reading.