← AXS-010

Circuit review & bench-test guide

AXS-010 — MAX31865 PT100 RTD front-end PMOD module

Document purpose#

This document explains the axs-010-max31865 module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC evidence in reports/.

This board has never been fabricated or assembled. The schematic is generated and ERC clean (0/0), and the netlist has been reviewed, but the PCB layout has not been started — there are no gerbers, no renders, and no physical board. Every number in this guide is a design target or a datasheet expectation to verify, not a measured result. Layout-dependent items — the analog front-end isolation from the PMOD bus, RREF placement, guard routing — cannot be reviewed yet and are flagged below. Because this is a precision analog module, more of the eventual truth lives in the unbuilt layout than on any other board in the sensor line.

1. What the board does#

AXS-010 is a PMOD Type 2A (expanded SPI) peripheral carrying a Maxim/Analog Devices MAX31865 resistance-temperature-detector (RTD) to digital converter (SSOP-20). The host FPGA or MCU supplies 3.3 V through the PMOD plug and talks 4-wire SPI (modes 1 or 3, up to 5 MHz). The MAX31865 forces a bias current through a series string of an on-board 400 Ω 0.1 % reference resistor (R1) and the external PT100, then returns a 15-bit ratio RTD/RREF — so the reading is pure ratiometric fixed-point arithmetic, independent of the exact bias current. ~DRDY on PMOD pin 7 paces conversions.

A 4-position terminal block (J2) accepts the PT100 in 2-, 3-, or 4-wire form, selected by the solder-jumper matrix JP3/JP4/JP5 (default as shipped: 2-wire). This is the arithmetic-heavy SPI lesson: read and write register access, ~DRDY-paced conversions, ratiometric scaling, and a Callendar–Van Dusen linearization on top of the SPI FSM.

Functional block diagram#

PMOD plug J1 (2x6 right-angle)
  6/12: 3V3 ──┬───────┬───────┐
              C1 100n  C2 100n │ (VDD + DVDD decoupling)
                               R4 10k
  1: CS_N ─────────────────────┴──> U1 ~CS (16)
  2: MOSI ─────────────────────────> U1 SDI (14)
  4: SCK  ─────────────────────────> U1 SCLK (15)
  3: MISO <── R2 100R ── RTD_SDO ── U1 SDO (17)
  7: ~DRDY <─ R3 100R ── RTD_DRDY ─ U1 ~DRDY (1)

  U1 analog front end:
    BIAS(4)=REFIN+(5) ──[R1 400R 0.1%]── REFIN-(6)=ISENSOR(7)
    FORCE+(8) ─┬─ JP3 ─ RTDIN+(10)      C3 100n across RTDIN+/-
    FORCE2(9) ─ JP5 (GND | FORCE+)      C4 10n  across FORCE+/-
    FORCE-(12) ─ JP4 ─ RTDIN-(11)
       │  │        │        │
      J2: 1 F+   2 S+    3 S-   4 F-  (PT100 terminal block)

Current path (datasheet SSOP topology): BIAS → RREF(R1) → ISENSOR → FORCE+ → external RTD → FORCE−, with RTDIN+/RTDIN− sensing the RTD voltage differentially and REFIN+/REFIN− sensing across RREF.

2. Safety and scope boundaries#

• Electrically benign to the operator: 3.3 V, a few mA. Hazards are to the part and to measurement integrity. Use standard ESD handling.
• Absolute-maximum VDD/DVDD is −0.3 V to +4.0 V (operating 3.0–3.6 V, with 3.3 V nominal). A 5 V PMOD socket or a mis-set bench supply destroys U1. Verify the rail before every first connection.
• Never drive CS/SCLK/MOSI (or back-drive MISO/~DRDY) above DVDD + 0.3 V, including while the module is unpowered.
• The analog inputs (FORCE/RTDIN/REFIN) are low-level precision nodes. Do not inject voltage into them; do not probe them with an unbuffered scope during a conversion — probe capacitance changes the reading.
• Use a known 0.1 % (or better) resistor as a fake RTD for bring-up, not a real PT100, until the digital path is proven. A 100 Ω 0.1 % part reads as a PT100 at 0 °C (see section 7) and removes the sensor as a variable.
• The 400 Ω reference resistor R1 is the calibration. Its 0.1 % tolerance and 25 ppm/°C drift set the accuracy ceiling; self-heating of R1 and of the PT100 are real error sources on a precision measurement.
• Passing DEVID-equivalent register checks and a fake-RTD reading is not a temperature calibration or an accuracy qualification.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V to PMOD pins 6/12, GND on 5/11. VDD (pin 3) and DVDD (pin 2) are the same 3.3 V net; C1/C2 charge.
2. R4 (10 kΩ) holds ~CS at 3.3 V while the host FPGA is unconfigured, so the SPI port stays deselected and U1 ignores bus noise.
3. On power-up all eight registers are at their POR state (Configuration 0x00 — VBIAS off, no conversions). No bias current flows and the RTD self-heats negligibly until the host enables VBIAS.
4. The host writes the Configuration register (write address 0x80). The canonical bring-up value is 0xC2 = VBIAS ON, auto conversion mode, fault status cleared, 60 Hz notch, 2/4-wire — see section 7. (Use 0xC3 for 50 Hz mains regions.) In auto mode VBIAS stays on and conversions run continuously at the 50/60 Hz rate.
5. ~DRDY (U1 pin 1, push-pull) pulses low when a fresh result is latched. It passes through R3 to PMOD pin 7; no pull-up is needed.
6. The host reads the RTD registers 0x01 (MSB) / 0x02 (LSB). The top 15 bits are the resistance ratio RTD/RREF; D0 of the LSB is a fault flag.
7. The host converts: R_RTD = (code / 32768) × R_REF, then applies the Callendar–Van Dusen inverse to get temperature.
8. On demand the host runs the fault-detection cycle (section 9E) and reads the Fault Status register 0x07.

4. Interfaces#

RTD terminal block J2 (Phoenix MKDS 1,5/4-5,08): 1 FORCE+, 2 SENSE+ (RTDIN+), 3 SENSE− (RTDIN−), 4 FORCE−.

SPI framing (datasheet Serial Interface section):

• SPI modes 1 and 3 (CPHA = 1; SCLK may idle low or high), MSB first, ≤ 5 MHz. SCLK is active only while ~CS is low.
• First byte is the register address: reads use 0x00–0x07, writes use 0x80–0x87. The address auto-increments while SCLK continues, so a burst read from 0x01 returns MSB then LSB in one ~CS frame.
• Data is transferred MSB first, one register per byte.

No dedicated test points exist; probe at J1, at the R1–R4 pads, and at J2. (Layout to-do: add probe-friendly pads on FORCE/RTDIN/REFIN before fab, kept short and guarded.)

5. Component-by-component review#

5.1 Converter and connectors#

5.2 Reference and analog filters#

5.3 Series protection and strap#

5.4 Decoupling and wiring-mode jumpers#

Wiring-mode truth table (also silkscreened): 2-wire = JP3+JP4 bridged, JP5 1-2, RTD across terminals 2-3; 3-wire = JP3 bridged, JP4 cut, JP5 2-3, leads on 1/2/3; 4-wire = JP3+JP4 cut, JP5 1-2, all four terminals used. The DATA_FORMAT 3-Wire config bit (D4) must match the jumper state.

Power flags #FLG01 (3V3) and #FLG02 (GND) are ERC-only, not physical parts. Every reference designator in the schematic is covered above (U1, J1, J2, R1–R4, C1–C4, JP3–JP5).

6. Datasheet summary and design interpretation#

Primary reference: MAX31865 datasheet (Maxim/Analog Devices). Check the revision and the exact orderable suffix before procurement.

Official reference: MAX31865 datasheet.

7. Expected values before bench testing#

None of these have ever been measured on this design — no board exists.

The canonical first sequence: config write then RTD read#

1. Write CONFIG:  MOSI 0x80, 0xC2   (VBIAS on, auto conv, clear faults, 60Hz)
2. Wait one conversion (>=52 ms at 60 Hz) OR watch ~DRDY fall.
3. Read RTD:      MOSI 0x01, then clock 2 dummy bytes.
   MISO -> RTD_MSB, RTD_LSB.  code = ((MSB<<8 | LSB) >> 1).  fault = LSB & 0x01.
4. R_RTD = code * 400 / 32768.   With a 100 ohm 0.1% resistor: code≈8192, R≈100Ω, 0°C.

Any resistance far from code/32768 × 400 with a known resistor points at R1 tolerance, a wiring-jumper error, or an SPI framing/mode fault. A stuck 0x0000 or 0xFFFF means MISO is dead (R2 open, SDO unsoldered, wrong mode, ~CS not asserted).

Reference math worked#

RTD/RREF is a 15-bit fraction of 32768. With R1 = 400 Ω:

R1's 0.1 % tolerance moves the apparent temperature by roughly ±0.25 °C near 0 °C directly, before any PT100 or wiring error — which is why R1 grade, not firmware, sets the accuracy floor.

8. Manual schematic and assembly review checklist#

Schematic/netlist items (reviewable now):

• U1 pin map against the datasheet: ~DRDY=1, DVDD=2, VDD=3, BIAS=4, REFIN+=5, REFIN−=6, ISENSOR=7, FORCE+=8, FORCE2=9, RTDIN+=10, RTDIN−=11, FORCE−=12, GND2=13, SDI=14, SCLK=15, ~CS=16, SDO=17, DGND=18. Confirm MOSI→SDI(14) and MISO←SDO(17) through R2 — a swapped SDI/SDO is the classic dead-read cause.
• Confirm REFIN+ ties to BIAS and R1 sits between REFIN+ and REFIN−; ISENSOR ties to REFIN− (low side of R1).
• Confirm the 3-Wire config bit will match the JP3/JP4/JP5 state in host code.
• Re-run reports/erc.rpt after any regeneration; it must stay 0/0.

Assembly items (for the eventual first article — none exists yet):

• Measure R1 with a 4-wire meter and record it; verify 0.1 % / 25 ppm part.
• Verify J2 terminal ordering (F+, S+, S−, F−) against the silkscreen.
• Confirm C4 is C0G (not X7R) and C3 placement across RTDIN.
• Layout gate (cannot pass today): analog front end guarded and kept away from the SPI bus and the 3V3 plane switching; RREF near U1 with a Kelvin connection; short FORCE/RTDIN runs; verify PMOD pin-1 against a physical host socket.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, exact supply voltage, the fake-RTD/PT100 identity and its measured resistance, mains region (50/60 Hz), equipment, and operator. Two host contexts: standalone (current-limited 3.3 V bench supply + SPI adapter, phases B–E) and PMOD host (FPGA/MCU providing 3.3 V, phase F). Standalone first.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 assembly checklist under magnification.
2. DMM 3V3→GND (J1 pin 6→5), both polarities: no hard short.
3. ~CS (pin 1) → 3V3 (pin 6): ≈ 10 kΩ (R4).
4. MISO (pin 3) / ~DRDY (pin 7) → U1 pads: ≈ 100 Ω. MOSI/SCK → U1 14/15: ≈ 0 Ω.
5. Measure R1 in-circuit context and confirm the jumper state matches the intended wiring mode (default 2-wire).

B. Standalone first power (current-limited bench supply)#

1. Bench supply 3.3 V (measure it — abs max 4.0 V), current limit 20–50 mA, output off. Wire + to J1 pin 6, − to pin 5.
2. Power on: no current-limit trip; quiescent digital current only (VBIAS is off at POR). Milliamps of bias current before any config write = solder fault or a stray short across R1.
3. Verify 3.3 V at C1/C2 pads and ~CS idling at 3.3 V through R4.

C. Standalone SPI bring-up (adapter, still on bench supply)#

Use any 3.3 V SPI master. Configure mode 1 or 3, ≤ 5 MHz (start at 1 MHz), MSB first, common ground.

1. Config write/readback: write 0x80,0xC2; read back 0x00 → expect 0xC2 (VBIAS on). Proves both MOSI and MISO paths and framing.
2. Fake-RTD read: install a 100 Ω 0.1 % resistor across J2 terminals 2-3 (2-wire). Run the section 7 sequence: expect RTD MSB ≈ 0x40, LSB 0x00, code ≈ 8192, R_RTD ≈ 100 Ω, 0 °C. Swap in 200 Ω → code ≈ 16384.
3. ~DRDY plumbing: in auto mode, scope PMOD pin 7 — it pulses low each conversion (~52 ms at 60 Hz). Confirms R3 and the push-pull output.
4. 50/60 Hz notch: compare noise with config 0xC2 (60 Hz) vs 0xC3 (50 Hz) under mains pickup; the matching notch should be quieter.

D. Real PT100 and wiring modes#

1. Connect a known PT100 (ideally with a reference thermometer) in 2-wire; read temperature and compare. Expect lead-resistance offset (each 0.39 Ω of lead ≈ +1 °C).
2. Reconfigure to 3-wire (JP3 bridged, JP4 cut, JP5 2-3, DATA_FORMAT 3-wire bit set) and 4-wire (JP3+JP4 cut, JP5 1-2, 3-wire bit clear). Lead-resistance offset should shrink toward zero in 3/4-wire.
3. Apply a known temperature step (ice point / boiling point with altitude correction, or a dry-block) and record error vs the reference.

E. Fault-detection cycle#

1. With a resistor installed, write the automatic fault-detection command (0x84 with VBIAS on), wait for D3:2 to self-clear, read Fault Status 0x07 → expect 0x00 (no faults).
2. Open the sensor (remove the resistor): the RTD LSB D0 fault bit sets and Fault Status shows D3/D2 (RTDIN−/FORCE− open, over/under-voltage). Confirm the host detects and clears it (write 0x82/fault-clear).
3. Short the sensor (0 Ω across RTDIN): expect an RTD-Low threshold flag if thresholds are programmed. Verify recovery.

F. PMOD-host context (FPGA/MCU provides 3.3 V)#

1. Measure the host socket rail: must be 3.3 V (abs max 4.0 V). Confirm the I/O bank voltage too.
2. Plug in with host unconfigured; verify ~CS reads 3.3 V at the module.
3. Reproduce the phase C/D ladder from the host SPI master: config write/read → fake-RTD read → ~DRDY interrupt → real PT100 → CVD linearization in HDL.
4. Scope the first host-driven frame; confirm mode 1/3 and ≤ 5 MHz.
5. Soak: stream conversions for 30+ minutes; re-read config each N frames (stays 0xC2), watch for drift beyond R1 tempco and self-heating.

G. Release-only tests#

Absolute-accuracy calibration against a reference thermometer / dry-block, R1 tempco characterization, self-heating quantification, 3-wire lead-resistance rejection at cable length, EMC on the real layout, and ESD belong to a separate qualification plan gated on a fabricated board.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful implementation of the MAX31865 datasheet application: a 400 Ω 0.1 % reference on the REFIN/BIAS/ISENSOR node, RTDIN/FORCE filters, both supplies on 3.3 V with 100 nF each, ~CS defended by a 10 kΩ pull-up, sensor-driven SDO and ~DRDY behind 100 Ω series resistors, and a clean 2/3/4-wire jumper matrix. The principal risks are that nothing physical exists yet — no layout, no board, no first-article data; that this is a precision analog measurement whose accuracy is set by R1's tolerance/tempco and by unbuilt layout (guarding, Kelvin reference, front-end isolation); the 4.0 V absolute-maximum rail with no 5 V tolerance; and the firmware discipline of right-shifting the fault bit, matching the 3-wire config bit to the jumper state, and choosing automatic vs manual fault detection given the C3/C4 filter time constant. The bring-up ladder — config 0xC2, fake-RTD 0.25-ratio read, ~DRDY, wiring modes, fault cycle, CVD linearization — is exactly the sequence the AruviX SPI master and RTD controller will need to reproduce.