← AXS-011

Circuit review & bench-test guide

AXS-011 — Photodiode light sensor PMOD module

Document purpose#

This document explains the axs-011-photodiode prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

The board is a schematic-complete prototype only: ERC is clean (0 errors / 0 warnings) and the netlist has been reviewed, but no PCB has been laid out, fabricated, or bench-verified. Every number below is a design target to verify on a first article, not proof that an assembled board works. Two datasheet-driven review findings in section 5/6 (comparator input bias current into a 1 MΩ node, and common-mode range) materially widen the expected-value ranges and must be resolved by measurement.

1. What the board does#

A 12-pin PMOD Type 1 (GPIO) module: a BPW34S PIN photodiode is reverse biased (cathode on 3V3) into a 1 MΩ load to GND, so the LIGHT_NODE voltage rises with brightness. An LMV7219 push-pull comparator slices that node against a threshold set by a Bourns TC33X 10 kΩ trimmer, producing the digital LIGHT output on PMOD pin 1. The raw analog node is also brought out on PMOD pin 2 (LIGHT_RAW) through 100 Ω so the user can scope the analog truth behind the digital bit (level L1 lesson).

Functional block diagram#

        3V3 ──┬────────────┬──────────────┬── C1 100nF ── GND
              │            │              │
         D1 BPW34S      RV1 10k        U1 LMV7219 V+
         (cathode up)   (track 3V3-GND)
              │            │
        LIGHT_NODE      LIGHT_TH (wiper)
              ├────────────┼──────► U1 +in / -in
         R1 1M            │            │
              │            │        LIGHT_CMP (push-pull out)
             GND          GND           │
                                     R2 100R
              LIGHT_NODE ── R3 100R ────┼──► PMOD pin 2  LIGHT_RAW
                                        └──► PMOD pin 1  LIGHT

2. Safety and scope boundaries#

• This is a 3.3 V logic module. Power it only from a PMOD host socket (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible socket) or a bench 3.3 V current-limited supply (50 mA limit is ample; the board draws ~1–2 mA, dominated by U1 and the trimmer string).
• Check plug orientation before first power (pin 1 is the rightmost pin of the upper row viewed from the module top with the connector toward you — Pmod spec 1.2.0 Figure 2, verified in PMOD-SPEC-NOTES.md).
• LIGHT_RAW has ~1 MΩ source impedance behind R3. Probe it only with a 10 MΩ DMM or a 10x scope probe, and expect the instrument itself to load the node by up to ~10 % (1 MΩ vs 10 MΩ). Never drive LIGHT_RAW from the host: it is an analog output, and a host push-pull driver fighting through R3 into the diode/load is out of scope.
• Optical tests use room light and a phone flashlight only. No laser sources; this guide's "bright" test is an LED flashlight at a few cm.
• The lux figures in this guide are estimates layered on a datasheet curve taken with a specific test illuminant. Silicon response to white-LED or fluorescent office light differs from the datasheet illuminant, so treat all lux-denominated numbers as order-of-magnitude targets, not calibration points.

3. Signal behavior and design intent#

1. Photocurrent in reverse-biased D1 flows from 3V3 through the diode into R1, so LIGHT_NODE ≈ I_photo x 1 MΩ while the diode stays reverse biased.
2. Using the fetched Vishay BPW34 datasheet: reverse light current is 75 µA typical at 1 klx (VR = 5 V), i.e. about 75 nA per lx, so the node gains roughly 75 mV per lx — the 1 MΩ load makes this a dim-light sensor. The linear range runs out near 3.3 V / 75 mV/lx ≈ 44 lx; above that the diode loses reverse bias and the node saturates at the rail.
3. In saturation the diode operates photovoltaically; its open-circuit voltage (350 mV typ at 1 mW/cm², 950 nm, per Vishay) lets LIGHT_NODE float up to ~0.35 V above 3V3 in strong light. U1's absolute-maximum input is (V+) + 0.4 V = 3.7 V, so this is inside ratings but with only ~50 mV of paper margin at the typical corner — verify on bench.
4. Typical office light (300–500 lx) therefore pins LIGHT_RAW at the rail; covering the diode drops the photocurrent to dark current (2–30 nA → 2–30 mV across R1) plus whatever U1's input bias current does (see the review finding below). The comparator becomes interesting only in the dim region below a few tens of lx.
5. U1 compares LIGHT_NODE (+in) against the RV1 wiper (−in). Output high = bright. Internal hysteresis is 7 mV typical — only ~0.1 lx-equivalent, so slow light changes near threshold may still chatter in time; the HDL lesson adds hysteresis-in-time.

Review finding: comparator bias current vs the 1 MΩ node#

The LMV7219 input bias current is 450–500 nA typical, 950 nA max at 25 °C, 2 µA max over temperature (TI SNOS458I). Through the 1 MΩ node impedance that is a 0.45–2 V equivalent offset on LIGHT_NODE — the same order as the entire signal range. The datasheet table gives magnitude, not direction, so the dark-state node voltage cannot be predicted from the datasheet alone: it may sit near 0 V or be lifted by a large fraction of a volt. This is the dominant error term of the whole design and the first thing the bench must measure (procedure C). The trimmer makes the design usable anyway — the threshold is set empirically against real conditions — but any lux-calibrated claim is unsupported.

Review finding: common-mode range#

The LMV7219 guaranteed input common-mode range is −0.2 V to VCC − 1.2 V, i.e. up to ~2.1 V at a 3.3 V rail. LIGHT_NODE saturates at ~3.3 V in normal light, and RV1 can set LIGHT_TH anywhere up to 3.3 V. Both inputs are inside absolute maximums, but comparator parameters are not guaranteed above 2.1 V. In practice such comparators keep switching with degraded specs; the bench must confirm no output inversion or chatter with both inputs near the rail (procedure D step 4), and threshold settings above ~2.1 V should be documented as outside the guaranteed region.

4. External interfaces#

No test points exist; probe resistor pads. The comparator side of R2 shows the raw comparator output; the node side of R3 is LIGHT_NODE itself.

5. Component-by-component review#

5.1 Sensing and comparison path#

5.2 Load, protection, and decoupling#

There is deliberately no capacitor on LIGHT_NODE: with 1 MΩ impedance even 10 pF gives a 10 µs time constant, and the diode's own 25–70 pF capacitance (Vishay, bias-dependent) already dominates the node's speed.

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

Assumptions: Vishay typ photocurrent (75 nA/lx), tungsten-equivalent lux, bias-current effect unknown (section 3 finding) — dark values especially are wide ranges to be narrowed by measurement.

8. Manual schematic and assembly review checklist#

• Confirm J1 pin-1 orientation and 3V3/GND on pins 6/12 and 5/11 (buzz to nets); see PMOD-SPEC-NOTES.md.
• Verify D1 polarity: cathode to 3V3 (reverse bias). The cathode mark on BPW34-family parts is small — inspect under magnification. A reversed diode still produces a light-dependent-looking board and is the classic silent fault here.
• Verify U1 orientation on SOT-23-5: pin 1 = OUT, pin 2 = V−, pin 3 = +IN, pin 4 = −IN, pin 5 = V+ (TI pinout, verified). Buzz +in to LIGHT_NODE and −in to the RV1 wiper — a swap inverts the board's logic.
• Confirm RV1 track ends go to 3V3 and GND and the wiper to LIGHT_TH.
• Measure R1 ≈ 1 MΩ (in circuit, expect near-nominal), R2/R3 = 100 Ω.
• Confirm nothing shades D1's clear package (relevant at layout review: README requires the diode clear of shadowing parts).
• Reconcile the BPW34S MPN vs footprint question from section 6 before any fab order.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host/supply, equipment, ambient light description, and operator with every capture.

A. Unpowered inspection and resistance tests#

1. Complete the checklist above under magnification.
2. Measure 3V3-to-GND resistance: expect ~10 kΩ (RV1 track) in parallel with everything else — i.e. roughly 10 kΩ; a reading far below 5 kΩ suggests a C1 or rail short.
3. Diode check across D1 (board unpowered): forward drop ~0.4–0.7 V in one polarity, open in the other, confirming orientation against the 3V3 net.

B. First power and static levels#

1. Power from a current-limited 3.3 V bench supply (50 mA limit) or the PMOD host. Confirm ~1–2 mA supply current.
2. DMM: RV1 wiper (LIGHT_TH) sweeps smoothly 0 to 3.3 V end to end with no dead zones or jumps.
3. Confirm LIGHT (pin 1) sits at a clean rail level (either state, depending on light and threshold) — not a mid-level, which would suggest U1 oscillation or a floating input.

C. LIGHT_RAW characterization (the analog truth)#

1. Ambient office light (describe/measure it; typical 300–500 lx): expect LIGHT_RAW ~3.3 V (saturated). Record the exact value; if it exceeds 3.4 V, note the photovoltaic excursion and check it stays below 3.65 V under the brightest available light.
2. Cover the diode completely (opaque tape or cap, not a finger — fingers transmit red light): record the dark value. This measurement resolves the bias-current unknown: near 0 V means bias current is small or flows into the pin; hundreds of mV means it lifts the node. Write the value into the record — every threshold recommendation depends on it.
3. Phone flashlight at ~5 cm: confirm hard saturation and the ceiling value.
4. Dim sweep: in a darkened room, vary distance to a small lamp and record LIGHT_RAW at several levels between dark and saturation; confirm the node moves smoothly through the 0–3.3 V range and, if a lux meter is available, estimate the actual mV/lx slope against the 75 mV/lx target.

D. Threshold-trimmer setup and trip verification#

1. Set the working point: with the diode in the dark state (covered), note LIGHT_RAW_dark; with it in the lit state you want to detect, note LIGHT_RAW_lit. Both from procedure C.
2. Set RV1 so that LIGHT_TH is midway between those two readings (DMM on the wiper while adjusting). With the calculated defaults this lands near 0.8–1.7 V (≈ 11–22 lx nominal trip using the 75 mV/lx Vishay-typ slope).
3. Verify tripping: cover/uncover the diode and confirm LIGHT toggles the right way (high = bright). Slowly dim (move the lamp away) and confirm a single clean transition; a burst of edges near threshold is expected within ~7 mV of node ripple — record its duration for the HDL hysteresis-in-time lesson.
4. VCM-region check: set LIGHT_TH above 2.5 V and put the board in bright light so both inputs sit above the 2.1 V guaranteed common-mode limit. Confirm the output still behaves monotonically (no inversion, no oscillation). Record; this closes the section 3 VCM finding for this unit only.
5. Return RV1 to the documented default setting and record the wiper voltage.

E. Host integration#

1. On the PMOD host, confirm the FPGA reads LIGHT on pin 1 and that an ADC-less fabric counter can see the chatter band near threshold (teaching demo sanity).
2. If sampling LIGHT_RAW with a downstream ADC module later: re-read the loading warning in section 2 — 1 MΩ source impedance needs a buffered or high-impedance, low-rate sampler.

F. Release-only tests#

Temperature behavior (dark current roughly doubles every ~9 °C per the Vishay curve; U1 IB grows to 2 µA), long-term trimmer stability, optical aging of the clear package, and any lux-calibrated claim require controlled lab conditions and the ams-OSRAM datasheet reconciliation from section 6.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture matches its teaching intent: one photodiode, one load, one comparator, with the analog node exposed for probing. The calculated scale factor (~75 mV/lx from the Vishay-typ 75 µA at 1 klx into 1 MΩ) makes this a dim-light/darkness discriminator — in ordinary room light LIGHT_RAW sits saturated at the rail, which is itself a good lesson but must be stated in the module documentation. The principal open risks are: the LMV7219 input bias current (up to 2 µA over temperature) against the 1 MΩ node, which can shift the effective threshold by volts-equivalent and must be measured on the first article; operation of both comparator inputs above the guaranteed 2.1 V common-mode limit in bright conditions; the unreconciled ams-OSRAM BPW34S MPN versus the fetched Vishay data and the SMD footprint; and the usual fact that no PCB, no assembly, and no bench result exist yet.