← AXS-015

Circuit review & bench-test guide

AXS-015 — APDS-9960 gesture/proximity/RGB PMOD module

Document purpose#

This document explains the axs-015-apds9960 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the APDS-9960 manufacturer datasheet.

The board is an unfabricated, schematic-only prototype: ERC is clean (0 errors / 0 warnings) and the netlist has been reviewed, but no PCB layout exists, no board has been built, and no bench measurement has ever been taken. Every numeric value in this guide is a verification target taken from the schematic or the datasheet — it is not a measured result and is not proof that an assembled board will work.

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended, I2C) module carrying a Broadcom APDS-9960: gesture engine (four directional photodiodes and a 32-dataset FIFO), proximity engine, and RGBC color/ambient-light engine in one optical package with an integrated 950 nm IR LED and factory-calibrated constant-current LED driver. The module uses the single-supply hookup: LEDA ties to 3V3 and LEDK returns through the internal LDR sink, so IR LED pulses (up to 100 mA at the default drive, more with boost) are drawn from the shared 3.3 V rail, buffered by a 10 µF bulk capacitor. The I2C address is fixed at 0x39. The open-drain interrupt reaches PMOD pin 1 as GESTURE_INT; two solder jumpers make the 4.7 kΩ bus pull-ups removable for chained-module use. All engine configuration and gesture decoding is host firmware.

Functional block diagram#

PMOD J1 (2x6, Type 6 ext.)
  6/12  3V3 ───┬──────────┬─────────┬─────────┬────────┬───────────────┐
               │          │         │         │        │               │
          C1 100nF   C2 10uF    R1 4.7k   R2 4.7k   R3 10k             │
          (VDD HF)  (IR LED       │ SDA_PU   │ SCL_PU   │              │
                     pulse       JP1 ═╗     JP2 ═╗      │              │
  5/11  GND ───┐     reservoir)  (cut to    (cut to     │              │
               │                  unchain)   unchain)   │              │
   3/9  SCL ───┼──────────────────────┼─────────┘       │              │
   4/10 SDA ───┼──────────────────────┘                 │              │
               v                                        │              │
        ┌─────────────────┐ VDD ── 3V3                  │              │
        │    APDS-9960    │ LEDA ─ 3V3 ─────────────────┼──────────────┘
        │       U1        │ LEDK ─┬─ LDR (internal      │
        │ fixed I2C 0x39  │       │   current sink,     │   R4 100R
        │ gesture+prox+   │      net LED_K              │      │
        │ RGBC + IR LED   │ INT (open drain) ── GST_INT ┴──────┴─> pin 1
        └─────────────────┘                                  GESTURE_INT

2. Safety and scope boundaries#

• This is a 3.3 V logic-only module. Never apply 5 V; the APDS-9960 absolute maximum on VDD and every pin is 3.8 V.
• IR LED: the integrated 950 nm emitter is invisible to the eye and is pulsed at up to 100 mA (up to 300% more with LED_BOOST). Duty cycles are small, but do not stare into the package at close range during proximity/gesture soak tests, and do not defeat the pulse timing in firmware experiments.
• Bench current limit: proximity/gesture operation draws short 100 mA LED pulses from the shared 3.3 V rail. Average current stays in the single-digit-mA range (datasheet power example: 3.76 mA average at 100 mA / 8 pulses / 16 µs), but an aggressively set bench current limit (tens of mA with fast response) can fold back on the pulses. Set the limit around 200 mA at 3.3 V; C2 supplies the instantaneous pulse charge (calculated droop ≈ 80 mV for 100 mA × 8 µs from 10 µF).
• LED_BOOST restriction on this board: the datasheet recommends separate VDD and VLEDA supplies when running LED_BOOST at 200%/300%. This module intentionally shares one 3.3 V rail, so treat LED_BOOST values above 150% as out of scope for this hardware unless a later revision splits the rails.
• ESD precautions; never touch or contaminate the optical windows (sensor and LED apertures).
• Do not hot-plug the PMOD connector during measurements; decide pull-up ownership before chaining modules (section 4).
• Passing these bench tests demonstrates prototype function only, not EMC, photobiological-safety, or environmental qualification.

3. Power and control sequence#

1. The PMOD host (or bench supply) applies 3.3 V (pins 6/12) and ground (pins 5/11). VDD and LEDA power up together; LEDK returns through the internal LDR sink (constant-current driver), per the single-supply reference hookup. Datasheet ranges: VDD 2.4–3.6 V, VLEDA 3.0–4.5 V — 3.3 V satisfies both, with only 0.3 V of VLEDA margin at the bottom if the rail sags.
2. After POR the device initializes (≈5.7 ms) and enters SLEEP: ~1 µA typical (10 µA max). I2C access temporarily wakes the core even with PON = 0.
3. R1/R2 (through JP1/JP2) hold SDA/SCL at 3.3 V; R3 holds the open-drain INT high.
4. Host sets PON (ENABLE 0x80 bit 0). The oscillator runs; the first engine enable after sleep incurs a ≈7 ms exit-sleep delay.
5. Enabling AEN runs the color/ALS engine (no IR LED, ~200 µA typical). Enabling PEN pulses the IR LED per PPULSE/PPLEN and CONTROL<LDRIVE> (default 100 mA, 8 µs — LED off-chip current flows 3V3 → LEDA → LED → LEDK/LDR → internal sink → GND, drawn from C2). Device-side current ~790 µA plus LED duty-cycle average.
6. Gesture mode arms when GEN is set and PDATA crosses GPENTH (or GMODE is forced to 1): the engine streams 4-byte U/D/L/R datasets into the 32-deep FIFO, asserting INT when GFLVL reaches the GFIFOTH threshold. The engine exits when all unmasked channels fall below GEXTH for GEXPERS cycles (GMODE clears).
7. INT is open-drain, active low, shared by all engines' maskable interrupt sources; R3/R4 deliver it to PMOD pin 1. Non-gesture interrupts clear via special "address-accessing" commands (PICLEAR 0xE5, CICLEAR 0xE6, AICLEAR 0xE7); gesture flags clear by draining the FIFO.

4. Interfaces#

PMOD pin map (J1, Type 6 extended)#

Pins 9/10 duplicate SCL/SDA for chaining a second I2C module.

Jumpers#

There is no address jumper: the APDS-9960 supports the single 7-bit address 0x39. Chain buses (JP1/JP2) for multiple modules.

Test points#

None are defined in the rev 0.1 schematic. Probe SCL/SDA/INT at the J1 pins and 3V3/GND at pins 6/5. A test pad on the LED_K net would make the LED pulse train directly observable — worth adding at layout.

5. Component-by-component review#

Every reference designator in the generated schematic is listed.

Wiring note: the schematic ties U1's LEDK (pin 4) and LDR (pin 3) together on net LED_K, and LEDA (pin 5) to 3V3 — exactly the datasheet's "connect LEDK to LDR pin when using internal LED driver circuit" hookup.

6. Datasheet summary and design interpretation#

Primary reference: APDS-9960 datasheet (Avago/Broadcom AV02-4191EN). Passives: Yageo RC thick-film series, Murata GRM188R71C104KA01D / GRM21BR61A106KE19L via murata.com capacitor search.

7. Expected values before bench testing#

All values are targets to verify, not measurements.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin 1 = SDA, 2 = INT, 3 = LDR, 4 = LEDK, 5 = LEDA, 6 = GND, 7 = SCL, 8 = VDD). A rotated part misroutes the LED driver pins.
• Verify LEDK and LDR are joined (net LED_K) and LEDA reaches 3V3 — the single-supply hookup. An open here is invisible to I2C tests and only appears as dead proximity/gesture.
• Verify JP1/JP2 bridged for standalone use; record chained-build intent.
• Measure R1, R2 (4.7 kΩ), R3 (10 kΩ), R4 (100 Ω) before power.
• Confirm C1 and C2 present, correct values, not cracked; either shorted is a rail short.
• At layout time (still open): C2 must sit immediately adjacent to U1's LEDA/VDD pins — this is the module's most placement-sensitive part; keep both optical windows (sensor and LED) free of mask/silk; the datasheet recommends an optical barrier between LED and sensor apertures if a window covers the module; consider a LED_K test pad.
• Confirm no solder bridges on J1, especially pins 3-4 and 5-6.
• Confirm #FLG01/#FLG02 are schematic-only (not in BOM or placement).

9. Ordered bench-test procedure#

Assume a PMOD host (FPGA board) or a 3.3 V bench supply current-limited to about 200 mA (see section 2 — pulsed LED current can trip an aggressive limit) wired to J1 pins 6/12 and 5/11, plus an I2C master on pins 3/4. Stop at the first abnormal result and record everything.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure 3V3→GND resistance in both meter polarities; investigate anything under ~10 kΩ before power.
3. Verify SDA→3V3 ≈ 4.7 kΩ, SCL→3V3 ≈ 4.7 kΩ, pin 1→3V3 ≈ 10.1 kΩ.

B. First power, no I2C traffic#

1. Apply 3.3 V at a 200 mA limit.
2. Confirm sleep current ≤ ~15 µA and SDA/SCL/pin 1 idle at 3.3 V.

C. Address-ACK scan#

1. Wait ≥10 ms after power-up (5.7 ms init), then scan all 7-bit addresses.
2. Expect an ACK only at 0x39. No ACK: U1 power/orientation/bus. Extra ACKs: another device on the chain.

D. First-transaction bring-up (ID and power-on)#

1. Read the ID register: START, 0x39+W, register 0x92, repeated START, 0x39+R, read one byte — expect 0xAB. If 0x9C or 0xA8 appears, record it, identify the part's provenance (these values are reported in the field for later silicon and clones but are not in the datasheet), and continue only with that caveat logged.
2. Write ENABLE (0x80) = 0x01 (PON). Wait ≥7 ms.
3. Read STATUS (0x93); expect the power-up pattern (0x04 reset value, PVALID/AVALID clear until engines run).
4. Confirm supply current is now in the idle/oscillator-on range (tens of µA, below the ALS-active 200 µA).

E. ALS engine and proximity engine (with LED-current check)#

1. Write ENABLE = 0x03 (PON | AEN). After ≥ one ATIME period (2.78 ms default; write ATIME 0x81 = 0xDB for 100 ms first for usable range), read CDATAL/H (0x94/0x95, low byte first) — expect nonzero room-light counts that fall when the sensor is covered. Supply current ~200 µA: the color engine must not produce LED pulses.
2. Enable proximity: write ENABLE = 0x05 (PON | PEN). Defaults give LDRIVE = 100 mA, PPULSE reset 0x40 = 8 µs / 1 pulse; optionally write PPULSE (0x8E) = 0x87 (8 µs, 8 pulses) for the datasheet's recommended condition.
3. IR LED current check: watch the supply. Expect a measurable average step (device ~0.8 mA plus LED duty average, order 1–4 mA depending on pulse settings) and, on a scope across the supply or at C2, brief ~100 mA pulse-train droop events (~80 mV calculated at C2). A phone camera (no IR filter) pointed at the module should show the LED flashing. If the bench supply folds back or the device resets here, raise the current limit — this is the anticipated aggressive-limit trip point.
4. Read PDATA (0x9C): expect ~10 counts (≤25) with nothing above the module, rising toward 96–144 with a hand/90% card at ~100 mm and saturating toward 255 as the hand approaches.
5. Verify the CONTROL (0x8F) LDRIVE field: write LDRIVE = 3 (12.5 mA, 0xC0 in bits 7:6) and confirm both the supply-current step and PDATA sensitivity drop; restore LDRIVE = 0. Do not test LED_BOOST above 150% on this shared-rail board (datasheet recommends split supplies for 200/300%).

F. Gesture-engine bring-up and FIFO behavior#

1. Configure before enabling (datasheet requirement):

• GPENTH (0xA0) = 0x28 (enter gesture when PDATA ≥ 40),
• GEXTH (0xA1) = 0x1E (exit below 30),
• GCONF1 (0xA2) = 0x40 (GFIFOTH = 1: interrupt at 4 datasets),
• GCONF2 (0xA3) = 0x41 (GGAIN 4×, GLDRIVE 100 mA, GWTIME 2.8 ms),
• GPULSE (0xA6) = 0x87 (8 µs, 8 pulses),
• GCONF4 (0xAB) = 0x02 (GIEN).

1. Write ENABLE = 0x4D (PON | PEN | WEN | GEN). The engine now arms via proximity: nothing should happen with no object present (GFLVL = 0, INT high).
2. Wave a hand a few centimeters above the module. Expect: GMODE sets (GCONF4 bit 0 reads 1), STATUS (0x93) GINT (bit 2) asserts, pin 1 falls, and GFLVL (0xAE) reads a climbing dataset count (1–32).
3. Drain the FIFO: for each GFLVL count read four bytes GFIFO_U/D/L/R = 0xFC/0xFD/0xFE/0xFF (a 4-byte burst per dataset). Expect all four channels to rise from the ~10-count no-object floor toward 100–255 and fall again as the hand leaves; for an up-to-down swipe the U and D waveforms are time-shifted copies (D leads on entry from the down side), and L/R shift for sideways swipes. GINT/GVALID clear once the FIFO is empty.
4. Leave the FIFO undrained during a long wave: GFLVL should peg at 32 and GSTATUS (0xAF) GFOV (bit 1) must set — confirming overflow detection. Clear with GCONF4 GFIFO_CLR (bit 2).
5. Confirm the engine exits after the hand leaves (GMODE clears) and that supply current returns to the idle level — a stuck GMODE (e.g. GEXTH = 0) keeps the LED pulsing indefinitely.

G. Interrupt line and pull-up chain configuration#

1. During F3, verify pin 1 (GESTURE_INT) falls below 0.4 V and recovers to 3.3 V after the FIFO is drained. For proximity interrupts, set PILT/PIHT (0x89/0x8B) around PDATA, set PIEN, and clear with the PICLEAR (0xE5) address-access command.
2. Power off. Cut JP1/JP2; verify SDA→3V3 and SCL→3V3 read open on this module alone; operate behind a pull-up-fitted module and repeat C–D; re-bridge and re-verify ≈4.7 kΩ.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic implements the standard single-supply APDS-9960 hookup (LEDA to 3V3, LEDK joined to the internal LDR sink) with the decoupling the arrangement demands: 100 nF for VDD plus a 10 µF reservoir for the 100 mA IR LED pulse train, and datasheet-conformant pull-ups on the bus and interrupt. The design's defining constraint is the shared rail: LED pulses draw from the same 3.3 V that powers the sensor core and the PMOD host, so C2's placement is the single most important layout decision still ahead, LED_BOOST above 150% is out of scope for this hardware, and bench supplies need a generous current limit despite the small average draw. The principal open risks are pre-fabrication: no PCB exists (optical apertures, LED-to-sensor crosstalk barrier, and C2 placement unverified), no board has ever been powered, and the gesture engine — the most stateful peripheral in the sensor line — has an entirely unwritten host driver whose FIFO-draining discipline this guide's section 9F is designed to prove out. The ID-register ambiguity (datasheet 0xAB versus field-reported 0x9C/0xA8) should be resolved against the actual purchased lot at incoming inspection.