← AXS-016

Circuit review & bench-test guide

AXS-016 — ADXL343 3-axis accelerometer PMOD module

Document purpose#

This document explains the axs-016-adxl343 module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and reports/erc.rpt.

This board has never been fabricated or assembled. The schematic is ERC clean (0/0, see reports/erc.rpt) and the netlist has been reviewed, but the PCB layout has not even been started — there are no gerbers, no renders, and no physical board. Every number in this guide is a design target or a datasheet expectation to verify, not a proven result. Layout-dependent items (decoupling placement, mechanical mounting stiffness, which matters for an accelerometer) cannot be reviewed yet and are flagged below.

1. What the board does#

AXS-016 is a PMOD Type 2A (expanded SPI) peripheral carrying an Analog Devices ADXL343 3-axis digital accelerometer (±2/±4/±8/±16 g, LGA-14). The host FPGA or MCU supplies 3.3 V through the PMOD plug and talks 4-wire SPI in mode 3 (CPOL=1, CPHA=1) at up to 5 MHz. INT1/INT2 on PMOD pins 7/8 expose tap, double-tap, activity, free-fall, data-ready, and FIFO events for interrupt-driven design exercises. The ADXL343's I2C fallback is deliberately not wired — this module is the SPI lesson (AXS-007 is the I2C lesson).

A 10 kΩ pull-up on ~CS keeps the part deselected (and therefore in its I2C idle posture, harmlessly, with no I2C master present) before the host FPGA configures its pins. The three sensor-driven lines (MISO, INT1, INT2) pass through 100 Ω series resistors per the AruviX miswire-tolerance rule.

Functional block diagram#

PMOD plug J1 (2x6, right-angle)
  6/12: 3V3 ──┬──────────┬───────────┬───────────────┐
              │          │           │               │
            C1 1uF    C2 100nF    C3 100nF        R4 10k
            (Vs bulk) (Vs HF)     (Vdd_I/O)          │
                                                     │
  1: CS_N ───────────────────────────────────────────┴──> U1 ~CS (pin 7)
  2: MOSI ──────────────────────────────────────────────> U1 SDI (pin 13)
  4: SCK  ──────────────────────────────────────────────> U1 SCLK (pin 14)
  3: MISO <── R1 100R ── ACC_SDO ─────────────────────── U1 SDO (pin 12)
  7: INT1 <── R2 100R ── ACC_INT1 ────────────────────── U1 INT1 (pin 8)
  8: INT2 <── R3 100R ── ACC_INT2 ────────────────────── U1 INT2 (pin 9)
  5/11: GND ──────────────── U1 GND (pins 2/4/5)
                             U1 Vs (6) + Vdd_I/O (1) on 3V3
                             RES pins 3/11 open per datasheet, pin 10 NC

2. Safety and scope boundaries#

• Electrically benign for the operator: 3.3 V, sub-milliamp. Hazards are to the part. Standard ESD handling; the datasheet carries an explicit ESD caution for this MEMS device.
• Absolute maximum Vs / Vdd_I/O is 3.9 V. Unlike the SHT31 module, there is no headroom story here: a 5 V PMOD socket or a mis-set bench supply can destroy U1 outright. Verify the rail before every first connection.
• Never drive CS/SCLK/MOSI (or back-drive MISO/INT1/INT2) above Vdd_I/O + 0.3 V, including while the module is unpowered.
• Mechanical shock rating is 10,000 g — bench handling will not hurt the MEMS, but do not hammer-test; tap tests with a fingertip are sufficient.
• Use a current-limited 3.3 V bench supply (≤50 mA limit is ample) for standalone tests; the module should draw ~0.1 µA in standby and ~145 µA measuring.
• Self-test and static-gravity numbers below are datasheet limits at stated supply voltages, not this board's measured behavior — nothing has ever been measured on this design.
• Passing DEVID and self-test is not a calibration or qualification claim.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V to PMOD pins 6/12, GND on 5/11. Vs (U1 pin 6) and Vdd_I/O (U1 pin 1) are the same 3.3 V net; C1/C2/C3 charge. The datasheet allows Vs and Vdd_I/O in any power sequence, and single-supply operation with Vs = Vdd_I/O is the documented simple case.
2. The ADXL343 powers up in standby (~0.1 µA typ): no measurements until the host sets the Measure bit. All registers are read/writable in standby.
3. R4 (10 kΩ) holds ~CS at 3.3 V while the host FPGA is unconfigured. With ~CS high the part treats the serial pins as I2C — harmless here because nothing drives SDA/SCL-shaped traffic — and, critically, ~CS never floats (the datasheet warns there is no default ~CS state and floating it may make the part unable to communicate).
4. Before the first transaction the host must idle SCLK high (mode 3) while ~CS is high, then drop ~CS, clock bytes on falling-edge-update / rising-edge-sample, and raise ~CS to end the transaction.
5. The host configures BW_RATE/DATA_FORMAT/interrupts in standby, then sets POWER_CTL Measure (bit D3). Data appears in 0x32–0x37 at the programmed ODR; INT1/INT2 (push-pull, active high by default) report events through R2/R3.

4. Interfaces#

SPI framing (datasheet Serial Communications section):

• Mode 3: CPOL=1, CPHA=1. SCLK idles high; SDI is updated on SCLK falling edges and sampled by the part on rising edges.
• Max SCLK 5 MHz at 100 pF bus loading; t_CS,DIS ≥ 150 ns between transactions; SDO valid ≤ 40 ns after SCLK falling edge.
• First byte: bit 7 = R/~W (0x80 = read), bit 6 = MB (0x40 = multibyte), bits 5:0 = register address. Address auto-increments while MB is set and clocks continue.
• ~CS must go low at the start and high at the end of every transaction; reads/writes of nonsequential registers need separate ~CS frames.
• 3-wire SPI exists (SPI bit D6 in DATA_FORMAT) but this module wires 4-wire and the SPI bit must stay 0.

No test points exist in the schematic; probe at J1 and at the R1–R4 pads. (Layout to-do: consider adding probe-friendly pads before fabrication.)

5. Component-by-component review#

5.1 Sensor and connector#

5.2 Decoupling#

Layout rule when the PCB is done: C2/C3 tight to U1 pins 6 and 1, low impedance ground return (datasheet Power Supply Decoupling section).

5.3 Series protection and strap#

Every reference designator in the schematic is listed above (U1, J1, C1–C3, R1–R4). There are no jumpers on this module.

6. Datasheet summary and design interpretation#

Primary reference: Analog Devices ADXL343 datasheet, Rev. 0 (product page: analog.com/ADXL343). The ADXL343 is register-compatible with the ADXL345, so ADXL345 material applies, but always verify against the ADXL343 sheet. Check the revision before procurement.

7. Expected values before bench testing#

None of these have ever been measured on this design — no board exists.

The canonical first read: DEVID over SPI mode 3#

Exact byte sequence (4-wire, mode 3, ≤5 MHz):

SCLK idles HIGH.  Assert ~CS low.
MOSI byte 0: 0x80        (R/~W=1 read, MB=0, address 0x00 = DEVID)
MOSI byte 1: 0x00 dummy  (MISO shifts out the register during this byte)
MISO byte 1: expect 0xE5
Deassert ~CS (high).  Keep ~CS high ≥150 ns before the next frame.

Any answer other than 0xE5 stops the bring-up. 0x00/0xFF = MISO dead (R1 open, U1 SDO unsoldered, wrong pin, ~CS not asserted); shifted values (0xCA, 0x72…) = wrong SPI mode or bit alignment.

Multibyte example — one atomic axis frame:

~CS low; MOSI: 0xF2 (0x80 read | 0x40 MB | 0x32), then 6 dummy bytes;
MISO returns DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1; ~CS high.
Each pair is twos-complement little-endian (x0 = LSB).

Self-test worked limits at 3.3 V#

Datasheet Table 15 gives self-test output-change limits at Vs = 2.5 V for ±2 g 10-bit or full-resolution mode; Table 14 scales them for supply (3.3 V: ×1.77 for X/Y, ×1.47 for Z). This design runs full-res ±16 g (DATA_FORMAT 0x8B during the test), where full-res keeps ~3.9 mg/LSB so the Table 15 LSB limits apply, scaled:

Per the datasheet: a part passes if at least the minimum magnitude of change is reached; exceeding the maximum is "not necessarily a failure" (the response is bimodal). Output needs ~4 samples to settle after toggling SELF_TEST, the part must be in normal power (LOW_POWER = 0), and ODR must be 100–800 Hz or 3200 Hz.

8. Manual schematic and assembly review checklist#

Schematic/netlist items (reviewable now):

• U1 pin map against datasheet Table 5: Vdd_I/O=1, GND=2/4/5, Vs=6, ~CS=7, INT1=8, INT2=9, NC=10, RESERVED=3 (Vs or open — open here), RESERVED=11 (GND or open — open here), SDO=12, SDI=13, SCLK=14.
• Confirm MOSI goes to SDI (pin 13) and MISO comes from SDO (pin 12) through R1 — a swapped SDI/SDO is the classic dead-DEVID cause.
• Confirm the SPI bit will be left 0 (4-wire) in all planned host code.
• ERC report reports/erc.rpt is clean; re-run after any regeneration.

Assembly items (for the eventual first article — none exists yet):

• Verify J1 pin-1 position and the PMOD zigzag numbering against the common library's PMOD_TO_HEADER map and a physical host socket (layout does not exist yet; this gate cannot be passed today).
• LGA-14 orientation mark and reflow quality (X-ray or angled inspection — leadless pads hide opens); no cleaning fluids trapped under the LGA.
• Measure R1–R4 and confirm C1/C2/C3 placement tight to U1 pins 6/1.
• Mechanical: U1 near a supported region of the board per the datasheet's mounting guidance; note board thickness/standoff plan in the record.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment, supply voltage (it changes the expected numbers), orientation fixture, and operator. Two host contexts are covered: standalone (current-limited bench supply + SPI adapter, phases B–D) and PMOD host (FPGA/MCU providing 3.3 V, phase E). Standalone first.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 assembly checklist under magnification.
2. DMM 3V3-to-GND (J1 pin 6 → 5), both polarities: no hard short.
3. ~CS (pin 1) → 3V3 (pin 6): ≈10 kΩ.
4. MISO (pin 3) / INT1 (pin 7) / INT2 (pin 8) → corresponding U1 pads: ≈100 Ω each. MOSI (pin 2) and SCK (pin 4) → U1 pins 13/14: ≈0 Ω.

B. Standalone first power (current-limited bench supply)#

1. Bench supply 3.3 V (measure it — abs max is 3.9 V), current limit 20–50 mA, output off. Wire + to J1 PMOD pin 6 (or 12), − to pin 5 (or 11), respecting the header zigzag mapping once a layout defines it.
2. Power on: no current-limit trip; standby draw ≈ 0.1 µA (sub-µA on the meter). Milliamps in "standby" mean a solder fault or a mis-set supply.
3. Verify 3.3 V at C1/C2/C3 pads, ~CS idling at 3.3 V through R4, INT1/INT2 near 0 V, MISO quiescent.

C. Standalone SPI bring-up (adapter, still on bench supply)#

Use any 3.3 V SPI master (FT232H, MCU devboard, logic-analyzer-plus-master). Common ground with the supply. Configure mode 3, ≤5 MHz (start at 1 MHz), MSB first. Ensure SCLK idles high before the first ~CS assertion — the datasheet requires ~CS high while clock polarity/phase are being changed.

1. DEVID: run the section 7 sequence (0x80, dummy). Expect 0xE5. Capture the waveform of this first frame regardless of result.
2. Register write/readback: write OFSX 0x1E = 0x7F (frame: 0x1E, 0x7F), read back (0x9E, dummy → 0x7F), then restore 0x00. Proves MOSI path and framing in both directions.
3. Configuration in standby: BW_RATE 0x2C = 0x0A (100 Hz, normal power); DATA_FORMAT 0x31 = 0x0B (FULL_RES, ±16 g, SPI bit 0, INT active high).
4. POWER_CTL measure sequence: write 0x2D = 0x08 (Measure). Supply current rises from ~0.1 µA to ~145–190 µA. Wait ≥ 11.1 ms (turn-on at 100 Hz). To return to standby later, write 0x2D = 0x00 — configure-in- standby / measure / clear-measure is the datasheet's recommended pattern.
5. Data read: multibyte frame 0xF2 + 6 dummies → DATAX0…DATAZ1. With the board flat and still: z ≈ +256 LSB (≈1 g), x/y ≈ 0 ± offset. Average ≥10 samples (0.1 s at 100 Hz, the datasheet's recommended starting point).
6. Six-orientation static test: rest the board on each face so each of ±x, ±y, ±z aligns with gravity. Expect ≈ ±265 LSB on x/y and ≈ ±256 LSB on z (3.3 V sensitivities), the other two axes near 0 (within offset ±35 mg-class + 3.3 V shifts + noise). Record all 18 averaged values; opposite-face pairs should be symmetric about the axis offset.
7. DATA_READY plumbing: INT_ENABLE 0x2E = 0x80, INT_MAP 0x2F = 0x00 (DATA_READY → INT1): INT1 (J1 pin 7) toggles at the ODR and clears on data reads; INT_SOURCE 0x30 confirms. Map to INT2 (0x2F = 0x80) and verify pin 8, proving R3.

D. Self-test (standalone, board stationary and flat)#

Datasheet "Using Self-Test" procedure, at Vs = 3.3 V:

1. Configuration: BW_RATE = 0x0A (100 Hz, LOW_POWER = 0), DATA_FORMAT = 0x0B (full-res, ±16 g), Measure on. Board must not move during the test.
2. Baseline: average ≥ 0.1 s (≥10 samples) of x/y/z → X_ST,OFF, Y_ST,OFF, Z_ST,OFF.
3. Enable: DATA_FORMAT = 0x8B (SELF_TEST | FULL_RES | ±16 g). Discard ~4 samples (settling), then average the same number of samples → X_ST,ON, Y_ST,ON, Z_ST,ON.
4. Disable: DATA_FORMAT = 0x0B; discard ~4 samples.
5. Compute X_ST = X_ST,ON − X_ST,OFF (same for Y, Z) and compare to the 3.3 V limits from section 7: X +89…+956, Y −956…−89, Z +110…+1286 LSB. Pass = at least the minimum magnitude with the correct sign; above-max is not automatically a failure (bimodal response) but record it.
6. Repeat once; the two runs should agree within noise. Log the exact supply voltage — the shift scales with Vs².

E. PMOD-host context (FPGA/MCU provides 3.3 V)#

1. Measure the host socket rail: must be 3.3 V (a 5 V PMOD socket destroys U1 — abs max 3.9 V). Confirm the host I/O bank voltage too.
2. Plug in with host unconfigured; verify ~CS reads 3.3 V at the module (R4 working against a floating host pin) and standby current if the host exposes rail measurement.
3. Run the same ladder from the host (bit-banged SPI or the AruviX HDL SPI master when it exists): DEVID 0xE5 → OFSX write/readback → configure → Measure → flat-orientation read → DATA_READY on INT1.
4. Hold ~CS high ≥150 ns between frames and respect mode 3 in the HDL; scope the first host-driven frame and compare against the phase C capture.
5. Interrupt exercise (module's teaching goal): configure single-tap (THRESH_TAP 0x1D ≈ 0x30 = 3 g, DUR 0x21 ≈ 0x10 = 10 ms, TAP_AXES 0x2A = 0x07, INT_ENABLE bit 6), tap the bench beside the board, observe INT1 and clear via INT_SOURCE reads. Then a FIFO stream + watermark run.
6. Soak: stream at 100 Hz for 30+ minutes; zero framing errors (DEVID re-read every N frames stays 0xE5), stable offsets to within temperature drift (±0.8 mg/°C class).

F. Release-only tests#

Sensitivity/offset calibration against a rate table or precision fixture, temperature characterization, 1.6/3.2 kHz-ODR high-speed SPI (≥2 MHz required per datasheet), vibration/mounting-resonance evaluation on the real layout, and ESD belong to a separate qualification plan, gated on a board existing at all.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful minimal implementation of the ADXL343 datasheet's application diagram plus AruviX line rules: both rails on 3.3 V with the prescribed 1 µF + 0.1 µF decoupling, ~CS defended by a 10 kΩ pull-up against the no-default-state warning, all three sensor-driven outputs behind 100 Ω series resistors, I2C deliberately unwired, and RES pins handled per Table 5. The principal risks are that nothing physical exists yet — no layout, no fabricated board, no first-article data; the LGA-14's inspection difficulty; the 3.9 V absolute-maximum rail with zero tolerance for 5 V host mistakes; SPI mode-3 discipline in host code (idle-high SCLK before first ~CS); and mechanical placement of U1 relative to board mounting, which cannot be judged until a layout exists. The bring-up ladder — DEVID 0xE5, register readback, configure-in-standby, Measure, ±1 g statics, scaled self-test — is exactly the sequence the AruviX Verilog SPI master will need to reproduce.