← AXS-021

Circuit review & bench-test guide

AXS-021 — Ultrasonic ranger carrier PMOD module

Document purpose#

This document explains the axs-021-ultrasonic PMOD carrier at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC report in reports/.

This board has never been fabricated. Repository status is schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started; not released. There is no PCB, no BOM export, no DRC record, and no first-article bench result. Every number below is a target to verify against real hardware, not a proven result.

1. What the board does#

The board is a passive PMOD carrier for a 3.3 V HC-SR04-form-factor ultrasonic ranger, intended to be the Adafruit RCWL-1601 (product 4007). The transducer module plugs upright into a 1x4 socket; the carrier adds the Digilent PMOD Type 1 (GPIO) interface, a TRIG pull-down, a series resistor on the module-driven ECHO line, and local decoupling. There is no active silicon on the carrier itself.

The FPGA host drives TRIG high for at least 10 µs; the module emits an 8-cycle 40 kHz burst and raises ECHO for a time proportional to the round trip: distance_cm = echo_high_us / 58.

Functional block diagram#

PMOD host (3.3 V)                 Carrier                    Plug-in module
┌──────────────┐        ┌───────────────────────┐        ┌────────────────┐
│ J1 pin 1 TRIG├───────>│ TRIG ──┬──────────────├───────>│ Trig           │
│              │        │        R2 10k         │        │                │
│              │        │        └── GND        │        │  RCWL-1601     │
│ J1 pin 2 ECHO│<───────│ ECHO ──R1 100Ω── ECHO_RAW <────│ Echo           │
│              │        │                       │        │  (40 kHz Tx/Rx │
│ 3V3 (6, 12)  ├───────>│ 3V3 ──┬──┬────────────├───────>│ Vcc  pair)     │
│ GND (5, 11)  ├────────│ GND   C1  C2          ├────────│ Gnd            │
└──────────────┘        │      100n 10µ         │  J2    └────────────────┘
                        └───────────────────────┘  1x4 socket

2. Safety and scope boundaries#

• Voltages are limited to 3.3 V, so electrical hazard is low, but a 5 V-only classic HC-SR04 module must never be fitted: the carrier provides a 3.3 V rail only, and an externally powered 5 V module would drive a 5 V ECHO into a 3.3 V host pin. See sections 6 and 9.F.
• The carrier has no level shifter, clamp diode, or TVS on ECHO. R1 (100 Ω) limits current but does not clamp voltage — do not rely on it as 5 V protection. This is a deliberate, documented limitation of the design (generate_design.py schematic comments), not a hidden safety feature.
• Standalone bench work must use a current-limited 3.3 V supply (≤100 mA limit is ample; the module draws ~2.2 mA typical).
• The 40 kHz burst is inaudible and at these power levels harmless, but do not point the transducer directly into an ear at close range for long sessions as a matter of practice.
• ERC-clean is a schematic check only. It proves nothing about a board that does not yet exist; layout, DRC, fabrication, and assembly quality are all unverified.

3. Signal and power sequence#

1. 3V3 and GND arrive from the PMOD host (pins 6/12 and 5/11) or the bench supply. C2 charges; C1 provides high-frequency decoupling at the socket.
2. With the host pin unconfigured (high-Z at FPGA configuration time), R2 holds TRIG at GND so the module cannot false-trigger.
3. The module (RCWL-1601) powers up and idles with ECHO low.
4. The host drives TRIG high for ≥10 µs, then low.
5. The module emits an 8-cycle 40 kHz transmit burst (~200 µs of drive); C2 buffers this brief current peak so the 3.3 V rail does not sag at the end of the PMOD cable.
6. ECHO goes high when the burst is sent and returns low when the reflection is received (or after an internal timeout, typically tens of ms, if nothing echoes back). The host times the high interval through R1.
7. Wait ≥60 ms before the next trigger so a late echo from the previous burst cannot corrupt the next measurement.

4. Interfaces#

PMOD pin map (Type 1 GPIO):

There are no test points defined yet (no layout exists); bench probing is at J1/J2 pins and passives.

5. Component-by-component review#

5.1 Connectors#

5.2 Line conditioning#

5.3 Decoupling#

#FLG01/#FLG02 are ERC power-flag symbols only — they place no physical part.

5.4 The plug-in module (in scope)#

6. Datasheet summary and design interpretation#

Official references: Adafruit RCWL-1601 product page (4007), Adafruit ultrasonic sonar distance sensors guide, classic HC-SR04 datasheet (SparkFun mirror, protocol reference), Murata GRM188R71C104KA01D, Murata GRM21BR61A106KE19L, Yageo RC thick-film series. Check the current revision before procurement; the RCWL-1601 itself has no formal manufacturer datasheet — Adafruit's product page and guide are the practical documentation.

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Verify J1 odd/even pin numbering against the Digilent PMOD spec on the first layout: 3V3 must land on PMOD 6/12 and GND on 5/11. A row swap here is the most dangerous plausible layout error.
• Verify J2 net order on the physical board matches HC-SR04 order: pin 1 = 3V3, 2 = TRIG, 3 = ECHO_RAW, 4 = GND. Buzz it out before any module is ever inserted.
• Confirm R1 = 100 Ω sits in the ECHO path and R2 = 10 kΩ from TRIG to GND — not swapped (a 10 kΩ in series with ECHO still works; a 100 Ω TRIG pull-down would load the host driver with 33 mA-class demands and is wrong).
• Confirm C1/C2 placement close to J2 in the eventual layout.
• Confirm silkscreen marks module orientation (VCC end) unambiguously.
• Confirm the schematic comment "5 V-only HC-SR04 modules must not be fitted" is carried onto the board silkscreen or at least the README that ships with the board.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, module identity (exact marking/vendor), equipment, and ambient conditions.

A. Unpowered inspection and resistance tests (no module fitted)#

1. Visual inspection under magnification: solder quality on J1/J2, R1, R2, C1, C2; no bridges.
2. DMM: 3V3-to-GND high resistance both polarities; TRIG-to-GND ≈ 10 kΩ; J1 pin 2 to J2 pin 3 ≈ 100 Ω; J2 pin 1 to J1 pin 6 ≈ 0 Ω; J2 pin 4 to J1 pin 5 ≈ 0 Ω.
3. Buzz every J2 pin to its intended net. Do not skip this — a reversed socket destroys the first module inserted.

B. Candidate-module qualification (BEFORE it ever touches the carrier)#

This is the mandatory 5 V-module screening test. Many "HC-SR04" modules are 5 V-only with a 5 V ECHO output; a genuine RCWL-1601 is 3.3 V-capable. Markings are not reliable — test electrically.

1. Power the bare candidate module from a current-limited 3.3 V bench supply only (50 mA limit). Confirm it draws a plausible ~2–3 mA.
2. Drive Trig with a 3.3 V 10 µs pulse (signal generator or a known-good 3.3 V dev board) and scope Echo.
3. Pass criteria: the module ranges (Echo width tracks a target moved by hand) AND Echo high level is ≈3.3 V. A module that does not range at 3.3 V, or ranges only when supplied 5 V, is 5 V-only — reject it for this carrier.
4. Never pre-qualify by powering the module at 5 V while its Echo is connected to anything 3.3 V.

C. Standalone carrier bring-up (bench supply, no host)#

1. With a qualified module fitted, connect a current-limited 3.3 V supply (100 mA limit) to J1 pin 6 (3V3) and pin 5 (GND). Confirm ~2–3 mA idle.
2. Scope TRIG at J2 pin 2: it must sit at 0 V (R2) with nothing driving.
3. Inject a 10 µs 3.3 V pulse into J1 pin 1 from a generator. Scope ECHO at J1 pin 2: a pulse appears whose width tracks target distance.
4. Verify the width math at measured distances: tape a target at 10 cm, 50 cm, and 1 m and confirm ≈580 µs / 2.9 ms / 5.8 ms within a few percent (temperature affects the speed of sound ~0.17 %/°C).
5. Scope the 3V3 rail AC-coupled during a burst; record droop.

D. Hosted bring-up (PMOD host providing 3.3 V)#

1. Plug the carrier into the FPGA PMOD port with the host unconfigured. Confirm no bursts occur (R2 holds TRIG low) — listen with a scope on ECHO for several seconds.
2. Load the trigger/echo timer core. Trigger single measurements first, then continuous at ≥60 ms intervals.
3. Cross-check fabric-computed distance against a ruler at 10/50/100 cm.
4. Sweep the repetition interval down below 60 ms deliberately and observe when readings become unstable (late echoes aliasing); document the safe floor, then return to ≥60 ms.
5. Test minimum range (expect a ~2–3 cm blind zone, unreliable below ~10 cm) and maximum range against a large flat target.
6. Test angular response: ±15–20° off-axis targets should still return.

E. Robustness checks#

1. Hot-plug behavior: insert/remove the module with carrier power on and confirm nothing latches or is damaged (low energy, but record it).
2. Long PMOD cable (if used): repeat D.3 and check rail droop and edge quality.

F. 5 V-module fault-mode awareness test (analysis + optional destructive test)#

What happens if a 5 V-only module is inserted anyway:

• Powered only from the carrier's 3.3 V rail: the module typically fails to range (no burst, or ECHO never rises). Annoying but harmless.
• Powered at 5 V externally with Trig/Echo on the carrier: its ECHO drives ~5 V into the host pin through only R1 (100 Ω). The carrier has no level shifter, no clamp, no TVS — generate_design.py confirms R1 is the only element in the path. Roughly (5 − 3.3 − V_diode)/100 Ω ≈ 10 mA is forced into the host I/O protection diode per pulse — above the continuous injection rating of many FPGA pins. This can degrade or destroy the host pin over time. Never do this. If mixed-voltage experiments are wanted, that is a different (future) carrier with a real level shifter.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The carrier is deliberately minimal and its schematic is coherent for the lesson it teaches: R2 makes the unconfigured-host state safe, R1 adds modest fault isolation on the one module-driven line, and C1/C2 address the transmit-burst current at the end of a PMOD cable. The design's single sharp edge is module selection: it is only safe with a genuinely 3.3 V-capable ranger (RCWL-1601), because the carrier intentionally has no level protection beyond 100 Ω of series resistance. The principal open risks are that no PCB exists yet (layout, J1 row order, and J2 pin order are all unbuilt and unverified), the plug-in qualification procedure must actually be followed for every candidate module, and every timing figure in section 7 is protocol-derived rather than measured.