← AXS-027

Circuit review & bench-test guide

AXS-027 — SPH0641LU4H-1 PDM microphone PMOD module

Document purpose#

This document explains the axs-027-pdm-mic PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, the shared PMOD conventions in ../../pmod-common/PMOD-SPEC-NOTES.md, and the Knowles SPH0641LU4H-1 datasheet cited in section 6.

This board is a schematic-complete prototype. It has NOT been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every frequency, current, and timing figure below is a design target computed from the schematic and the datasheet — evidence to verify on the first article, not proof that a board works.

The catalog named the MP34DT06; the design substitutes the Knowles SPH0641LU4H-1 (same 1-bit PDM class). All numbers in this guide come from the Knowles datasheet, not the ST part.

1. What the board does#

A single bottom-port PDM MEMS microphone. The host drives CLK; the mic answers with a 1-bit pulse-density-modulated stream on DATA, driven during one clock half-cycle and tri-stated during the other (selected by the JP1 SELECT strap), so two oppositely-strapped modules can share one DATA line for stereo. The FPGA lesson (L4) is building the CIC decimator plus droop-compensation FIR that turns the 1-bit stream back into PCM audio.

There is no analog output and no register interface: two wires, one clock domain, everything else is fabric DSP.

Functional block diagram#

                       3V3 ────────┬────────────┐
                                   |            |
                              C1 100nF     U1 SPH0641LU4H-1
                                   |        (PDM MEMS mic,
 PMOD J1                          GND       bottom port)
 pin 3  CLK  ──────────────────────────────> CLOCK
 pin 1  DATA <── R1 100R ── MIC_DATA ─────── DATA (driven on the
                                            |     strapped half-cycle,
 JP1 SELECT strap:                          |     Hi-Z otherwise)
   1-2 GND (default) = drive on CLK-low ──> SELECT
   2-3 3V3           = drive on CLK-high

2. Safety and scope boundaries#

• 3.3 V only, from a PMOD host socket or a bench 3.3 V supply with the current limit at or below 20 mA. Expected draw is under 1 mA.
• The mic is a bottom-port MEMS device: never poke, vacuum, blow compressed air into, or wash over the port hole (datasheet handling rules). Board wash after reflow is prohibited for the assembled module.
• CLK is the only host-driven line. DATA is module-driven through R1; do not configure the host DATA pin as an output.
• Do not drive CLK while VDD is absent, and observe the mode map: the datasheet forbids powering up into ultrasonic mode and waking from sleep directly into ultrasonic mode. Bring the mic up in standard mode (1.024–2.475 MHz) first.
• The datasheet clock rise/fall spec (t_EDGE) is 3 ns max — drive CLK from a proper 3.3 V CMOS output (FPGA pin), not a slow-edged function generator through long leads.
• A working audio capture is not an acoustic calibration and no EMC/ESD/environmental claim follows from it.

3. Power and signal path#

1. 3V3 arrives on J1 pins 6/12, GND on 5/11. C1 (100 nF) decouples the mic VDD — the datasheet's recommended bypass, and it must not be a Class 2 dielectric compromise placed far from the part (layout note).
2. At power-up with no clock the mic idles; DATA is high-impedance. The datasheet allows up to 50 ms power-up time.
3. The host drives CLK. The clock frequency selects the operating mode (this mic has no register map — frequency IS the mode control): sleep at or below 250 kHz, low-power 351–815 kHz, standard performance 1.024–2.475 MHz, ultrasonic 3.072–4.8 MHz. Frequencies in the gaps (816 kHz–1.023 MHz and 2.476–3.071 MHz) are unspecified — do not park the clock there.
4. With SELECT strapped to GND (JP1 1-2, default), the mic asserts DATA on the falling CLK edge (valid t_DD = 18–40 ns after the edge) and tri-states after the rising edge (t_DZ = 3–16 ns): it owns the clock-LOW half-cycle. Strapped to VDD it owns the clock-HIGH half-cycle. The host latches mic(low) data on the rising edge.
5. R1 (100 Ω) is series protection on the mic-driven DATA line, per the sensor-line rule for module-driven pins.
6. In fabric, a CIC decimator (typically R = 64) followed by a droop-compensation FIR recovers PCM at f_CLK / R.

Why SELECT must never float#

The SELECT pin is internally pulled low but the datasheet explicitly says it "should not be left floating." JP1 bridged 1-2 (GND) is the default; verify the strap is actually bridged at assembly review, because an open strap leaves the pin on a weak internal pull in violation of the datasheet note.

4. Interfaces#

Custom PDM map (neither SPI nor I2C type — PDM is clock out, data in), documented in the README. Pin 1 is the upper-row rightmost pin viewed from the module top with the connector toward you (PMOD-SPEC-NOTES).

No dedicated test points exist yet — the PCB is not laid out. Probing is at J1 pins and component pads.

5. Component-by-component review#

Every reference designator in the generator is covered.

6. Datasheet summary and design interpretation#

Datasheet actually fetched and read for this review (retrieved 2026-07-14): Knowles SPH0641LU4H-1 product datasheet, Revision B (04/06/2015) — fetched from the DigiKey mirror; the knowles.com URL recorded in generate_design.py returned 404 at review time. Confirm the current revision on knowles.com before procurement.

7. Expected values before bench testing#

All values are design targets from the schematic and datasheet.

8. Manual schematic and assembly review checklist#

• Verify U1 LGA-5 orientation (pin 1 = DATA; the datasheet marking diagram shows pin 1 adjacent to the port) and that the PCB port hole aligns with the package port and is kept clear of paste, pour, and soldermask web (layout item — the recommended land pattern is in the datasheet).
• Confirm JP1 is bridged 1-2 (SELECT = GND) and not double-bridged.
• Confirm C1 is placed immediately at U1 VDD (layout item) and is X7R.
• Measure R1 = 100 Ω in circuit.
• Confirm no board wash / no ultrasonic cleaning is specified in the assembly notes for this module.
• Verify J1 pin-1 orientation against PMOD-SPEC-NOTES.
• Fix the "1–3.2 MHz" text in generate_design.py and README to the datasheet's 1.024–2.475 MHz standard-mode range (finding, section 6).

9. Ordered bench-test procedure#

Bench context: either (a) a PMOD host — AruviX ECP5 rev-A or any 3.3 V Digilent-compatible PMOD socket — driving CLK from fabric, with a logic analyzer (>= 25 MS/s) and scope on pins 1/3, or (b) a bench 3.3 V current-limited supply plus a clean 3.3 V CMOS clock source (an FPGA dev board still being the practical choice given the 3 ns edge spec) and DMM/scope/logic analyzer. Stop at the first abnormal result.

A. Unpowered inspection and resistance#

1. Complete the checklist in section 8.
2. Measure 3V3-to-GND resistance both polarities; investigate a hard short.
3. Confirm DATA-to-GND and DATA-to-3V3 are not shorted (should read open; the mic output is Hi-Z unpowered).

B. First power, no clock#

1. Apply 3.3 V, current limit 20 mA. Wait 100 ms (power-up spec is 50 ms).
2. Record supply current. With no clock the mic settles toward sleep-mode current: expect on the order of 80 uA (plus board leakage). Milliamps here mean a short or a damaged part.
3. Verify DATA reads as a floating/Hi-Z node (a 1 MΩ scope input drifts; a logic analyzer shows an indeterminate level). There is no pull on DATA on this module by design — note for the host: enable a weak FPGA pull-down on the DATA pin, or expect garbage between clock edges at bring-up.

C. PDM clock/data capture (the core electrical test)#

1. Drive CLK at 2.4 MHz (standard mode; the datasheet's own test frequency), 50% duty, from the FPGA. Wait 15 ms (wake-up spec).
2. Scope CLK at J1 pin 3: confirm levels (>= 2.31 V high, <= 0.99 V low), duty inside 40–60%, and clean fast edges.
3. Two-channel scope capture, CLK on CH1, DATA on CH2, 100 ns/div: a correct capture with SELECT = GND shows DATA transitioning shortly after each CLK FALLING edge (valid within 18–40 ns) and releasing to Hi-Z just after each CLK RISING edge (3–16 ns). During the clock-HIGH half-cycle the line floats — on a scope this shows as a drifty mid-level ramp unless the host pull is enabled. This half-cycle ownership is the signature of the wired L/R select; if DATA instead changes on rising edges, JP1 is strapped to VDD or mis-bridged.
4. Logic analyzer capture (sample >= 25 MS/s, i.e. >= 10x oversample; latch DATA on the CLK rising edge): record at least one second of the bitstream in a quiet room. Compute ones-density: expect about 50% (datasheet DC output = 0 %FS). Density stuck at 0% or 100% means a dead/shorted DATA line, wrong SELECT phase, or a clock out of range.
5. Raw PDM density modulation test: whistle a steady tone about 30 cm from the port while capturing. Zoomed out, the captured density (running average over, say, 128 bits) must visibly oscillate at the whistle frequency around the 50% silence level. Louder = deeper density swings (increasing sound = increasing density of 1s on positive pressure). This proves the acoustic path (port hole open, MEMS alive) with no fabric DSP at all.
6. Sweep CLK across the standard band: 1.024, 1.536, 2.048, 2.475 MHz. The stream must stay live at all four. Then stop the clock, wait 10 ms (fall-asleep spec), confirm current drops toward sleep level, restart at 1.024 MHz and confirm data returns within 15 ms (wake-up spec).

D. CIC-core smoke test (fabric integration)#

Uses the platform pdm_cic core (Phase 0 HDL library) on the ECP5 host.

1. Configure: f_CLK = 2.048 MHz, CIC decimation R = 64 -> expected output sample rate f_s = 2.048 MHz / 64 = 32.0 kHz exactly (verify with a fabric counter against the board oscillator; a mismatch means the decimator drops samples).
2. Silence check: in a quiet room, the decimated output must sit near signed zero (mid-scale) with only noise-floor wander. A large fixed DC offset indicates a wrong CIC bit-growth/truncation or a stuck PDM input (density 0/100% folds to full-scale DC).
3. Whistle test: whistle an approximately steady 1–2 kHz tone. The decimated stream (dumped over UART or plotted from a level-meter demo) must show a clean visible sine at the whistled frequency. CIC passband droop makes higher frequencies read slightly low until the compensation FIR is enabled — a few dB at the band edge is expected, not a fault.
4. Level sanity: speech at normal effort about 30 cm away is roughly 65 dB SPL; with sensitivity -26 dBFS at 94 dB SPL, expect peaks in the ballpark of -55 dBFS. Exact SPL is uncalibrated on a bench — treat this as an order-of-magnitude check, not a spec measurement.
5. Optional stereo exercise: add a second module strapped 2-3 (VDD). Sharing one DATA line, the two mics interleave half-cycles; the fabric demultiplexes on opposite CLK edges. Verify neither drives during the other's half (scope for contention glitches at the edges).

E. Ultrasonic stretch exercise (optional, after C/D pass)#

1. With the mic already running in standard mode, move CLK to 3.072 MHz (never power up directly into this mode). Duty must tighten to 48–52%.
2. Decimate by 64 -> f_s = 48 kHz with an ultrasonic-shaped response, or by 32 -> 96 kHz for actual ultrasonic work. Verify the stream stays live and silence density remains about 50%.
3. Confirm supply current rises toward the 845 uA typical ultrasonic figure.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is minimal and correct for its purpose: the datasheet's interface circuit is exactly one bypass capacitor plus the SELECT strap, and the module adds only the platform's 100 Ω series-protection rule on the mic-driven line. The JP1 default (SELECT = GND, drive on clock-low) is consistent between the generator, the README, and the datasheet's mic(low)/mic(high) table, and it composes correctly into the two-module stereo exercise. Two findings: (1) the documented "1–3.2 MHz standard mode" range is wrong — the datasheet standard mode is 1.024–2.475 MHz, with 2.476–3.071 MHz unspecified and ultrasonic starting at 3.072 MHz; correct the generator text and README, and keep the host clock plan inside the real bands. (2) DATA has no board-level pull, so the shared-bus idle level is the host's responsibility — document the required FPGA pull-down in the HDL deliverable. The real risks on this module are not electrical but mechanical/assembly: the bottom port must survive layout (hole clearance), paste, and cleaning. Nothing is bench-verified yet; every number above is a first-article target.