← AXS-029

Circuit review & bench-test guide

AXS-029 — Stereo ICS-43434 I2S microphone-pair PMOD module

Document purpose#

This document explains the axs-029-stereo-mics prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

This board is a schematic-complete prototype only. It has not been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every numeric value below is a design target derived from the schematic and the manufacturer datasheets, not a measurement from real hardware. Datasheet figures cited here were verified against the fetched TDK InvenSense ICS-43434 datasheet (DS-000069, revision 1.0); see Section 6.

1. What the board does#

Two TDK InvenSense ICS-43434 24-bit I2S MEMS microphones share one I2S bus using slot multiplexing. The host FPGA drives SCK and WS to both microphones in parallel; each microphone drives the shared SD line only during its own hard-wired stereo slot (U1: LR pin to GND, left/WS-low slot; U2: LR pin to 3V3, right/WS-high slot) and tri-states otherwise. The module is a PMOD Type 7 (I2S) plug, 3.3 V only, host-clocked. There are no jumpers: the slot assignment is fixed by copper.

The teaching goals are stereo capture, tri-stated bus sharing, interaural delay measurement, and delay-and-sum beamforming in fabric. The layout target (not yet realized) is 10 cm microphone spacing.

Functional block diagram#

PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible socket)
   |
   J1 (PMOD Type 7 plug)
   |  pin 1  WS  (LRCLK, host out) ----+---------------------+
   |  pin 4  SCK (BCLK,  host out) ----|----+----------------|----+
   |  pin 3  SD  (ADC data, mic out) <-+    |                |    |
   |            ^                      v    v                v    v
   |            R1 100R          +-----------+          +-----------+
   |            |                | U1        |          | U2        |
   |    MIC_SD -+---------+------| ICS-43434 |          | ICS-43434 |
   |            |         |      | LR = GND  |          | LR = 3V3  |
   |            R2 100k   +------| SD (tri)  |     +----| SD (tri)  |
   |            |         |      +-----------+     |    +-----------+
   |           GND        +------------------------+
   |                          shared MIC_SD net
   +-- pins 5/11 GND, pins 6/12 3V3 --> C1, C2 (100 nF at each mic)

2. Safety and scope boundaries#

• This is an unfabricated design. Nothing in this guide is evidence that an assembled board meets these targets; the first assembled article must run the full procedure in Section 9.
• 3.3 V logic only. The ICS-43434 absolute maximum supply is 3.63 V and digital pins are limited to VDD + 0.3 V; never connect a 5 V host or 5 V logic analyzer pod drive to this module.
• Do not drive SCK/WS into the module while 3.3 V is absent. The datasheet warns that clocking an unpowered ICS-43434 continuously conducts through the ESD diodes and can degrade long-term reliability.
• The microphones have bottom-facing acoustic ports. Do not poke the port hole, apply vacuum pickup over it, blow compressed air into it, or board- wash an assembled module without a port-safe process; MEMS diaphragms are mechanically fragile even though rated 10,000 g shock.
• The parts are ESD-sensitive (HBM class per datasheet ESD caution). Use a grounded mat and strap for assembly and probing.
• Keep total module draw within the PMOD guidance of roughly 100 mA (PMOD-SPEC-NOTES.md); this design's ~1 mA budget is far inside it.
• Acoustic tests below are engineering checks, not calibrated acoustic measurements. Sensitivity/SNR verification against the datasheet requires a calibrated source and anechoic conditions that a normal bench lacks.

3. Signal and power sequence#

1. The host socket applies 3.3 V on J1 pins 6/12 and GND on pins 5/11. C1 and C2 provide the local decoupling the datasheet calls for (0.1 uF at the VDD pin of each microphone).
2. With no clocks, both microphones idle; once SCK falls below roughly 200 kHz (or is stopped) the parts are in standby/sleep (datasheet sleep current 12 uA typical each). R2 holds the released SD bus at 0.
3. The host starts SCK and WS with WS = SCK/64. Within the high-performance sample-rate window (WS 23 to 51.6 kHz) both microphones wake; output is within 1 dB of final sensitivity in at most 20 ms.
4. Both microphones sample acoustics synchronously at the WS falling edge (datasheet "Synchronizing Microphones"), which is what makes the stereo pair phase-comparable.
5. During the WS-low half-frame U1 drives 24-bit two's-complement data MSB-first, with the MSB delayed one SCK from the WS edge (standard I2S). SD tri-states immediately after the LSB, so U1 actively drives only SCK cycles 2-25 of its 32-cycle slot.
6. During the WS-high half-frame U2 does the same. In the undriven tail of each slot (cycles 26-32) and whenever both mics are tri-stated, R2 (100 kOhm, exactly the datasheet-recommended bus pull-down) bleeds the line toward 0.
7. R1 (100 Ohm) sits between the shared MIC_SD net and J1 pin 3, the sensor-line series-protection rule for every module-driven pin.

Why slot sharing works (and what would break it)#

The ICS-43434 SD pad is specified to tri-state when not actively driving its channel (t_SDD max 76 ns after the relevant SCK edge). Two outputs may therefore share one net only because their drive windows are disjoint halves of the WS frame. If both LR straps were accidentally wired to the same level, both parts would fight over the same slot: overlapping push-pull drivers, contention current on every disagreeing bit, corrupted data, and possible long-term damage. Verifying the two LR straps is therefore a first-article priority, not a formality.

4. Interfaces and pin map#

Bench contexts: either a PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible PMOD socket) driving real I2S clocks, or a bench 3.3 V current-limited supply plus DMM/oscilloscope/logic analyzer with a signal generator standing in for SCK/WS.

Per PMOD-SPEC-NOTES.md, this is the corrected Type 7 mapping (1 = LRCLK, 3 = ADC data, 4 = BCLK); module pin 1 is the rightmost pin of the upper row viewed from the module top with the connector toward you.

There are no test points in the schematic. Until layout adds them, probe at the J1 pins, the R1/R2 junction (MIC_SD), and each microphone's LR pad.

5. Component-by-component review#

ICS-43434 key datasheet parameters (verified from DS-000069 rev 1.0)#

6. Datasheet summary and design interpretation#

Two documentation notes. First, the generator embeds the original invensense.tdk.com datasheet URL, which now redirects/403s; the fetched copy above is the same document number (DS-000069) at revision 1.0, while the generator names v1.2 — re-verify against v1.2 before release in case a limit moved. Second, the README/schematic note "SCK 0.5-3.6 MHz" is slightly wider than the rev 1.0 SCK-period limits (about 0.4-3.3 MHz); treat the datasheet numbers as authoritative until v1.2 is checked.

7. Expected values before bench testing#

Example clock plan used throughout: SCK = 3.072 MHz, WS = 48 kHz.

8. Manual schematic and assembly review checklist#

• Verify J1 pin-1 orientation against PMOD-SPEC-NOTES.md Figure-2 rules (upper-row rightmost, square pad) before anything is powered.
• Buzz U1 pin 2 (LR) to GND and U2 pin 2 (LR) to 3V3. This is the single most important continuity check on the board; a swap breaks stereo identity, and a duplicate breaks the bus.
• Buzz both U1 pin 6 and U2 pin 6 (SD) to the shared MIC_SD net, MIC_SD through R1 (100 Ohm) to J1 pin 3, and MIC_SD through R2 (100 kOhm) to GND.
• Buzz WS (J1 pin 1) to both pin 1s and SCK (J1 pin 4) to both pin 4s.
• Confirm C1/C2 sit hard against each mic's VDD pin (layout review item) and measure 3V3-GND resistance for shorts before power.
• Confirm the two acoustic port holes in the PCB are open, unplugged by paste or mask, and match the land-pattern keep-outs (layout/fab review).
• Confirm reflow followed the datasheet's microphone soldering profile and that no board wash reached the ports (assembly review).
• Confirm J1 pins 2 and 7-10 really are NC.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record captures with board serial, host/equipment IDs, thresholds, ambient noise conditions, and operator.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND resistance in both meter polarities; investigate any hard short before power.
3. Measure J1 pin 3 to GND: expect about 100.1 kOhm (R1 + R2). Grossly low readings suggest a solder bridge on the SD net.
4. Verify the two LR straps one more time with the board in hand.

B. First power, no clocks (bench supply context)#

1. Feed 3.3 V from a current-limited bench supply (set the limit to about 20 mA) into J1 pins 6/12 vs 5/11.
2. Expect only tens of uA once settled (both mics asleep without clocks). Milliamps at this stage means a fault; stop and inspect.
3. Confirm SD sits at 0 V.

C. Clock bring-up and framing capture (PMOD host or generator)#

1. Attach to the PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible socket). Configure the fabric to output SCK = 3.072 MHz and WS = SCK/64 = 48 kHz, receive-only on SD.
2. Confirm supply current rises to roughly 1 mA and wait 20 ms (wake-up) before trusting data.
3. Scope SCK and WS: check frequency, the exact /64 ratio, and clean monotonic edges at the module (the mics tolerate 40-60% SCK duty and need rise/fall under 25 ns per the datasheet).
4. Logic-analyzer capture of SCK/WS/SD, threshold ~1.65 V, I2S decode: 24-bit words, MSB one SCK after each WS edge, 32 SCK per slot, 64 per stereo frame. Verify data changes on SCK falling and is stable on SCK rising (host sampling edge).

D. L/R slot verification and SD bus-sharing checks#

1. Slot ownership. Firmly cover (or gently rub a fingertip over the board area above) U1's port while playing ambient sound. The WS-low (left) words should collapse toward the noise floor while WS-high (right) words stay live. Repeat with U2 covered and confirm the mirror result. Tapping very near one mic gives the same discrimination with a sharper signature. This proves U1 owns left and U2 owns right, i.e. the LR straps match the design intent.
2. Tri-state behavior. Scope SD during the tail cycles (26-32) of each half-frame: the line must show a released, slowly-decaying level toward 0 through R2, not an actively driven value. With one mic's slot silent (port covered, data near zero) its slot bits still show active drive of near-zero codes during cycles 2-25 - that is correct; only the tail is released.
3. Bus contention screen. Watch supply current and the SD waveform across both WS edges. Contention shows up as current spikes aligned with slot boundaries, mushy intermediate voltage levels on SD (neither VOL nor VOH), or excessive heating of either mic. Any of these is a stop-and-fix: recheck the LR straps first.
4. Confirm both slots idle to 0 within a few tail cycles; if the decay through 100 kOhm is too slow for the host's decode of the next slot's leading zero, note it - the datasheet sanctions dropping the pull-down to 10 kOhm.

E. Stereo phase and interaural-delay test (one source)#

1. Place a single small sound source (phone speaker playing a 1 kHz tone, or a repeated sharp click) on the perpendicular bisector of the two microphones, equidistant from both. Capture simultaneous L/R sample streams in fabric.
2. Cross-correlate L against R (an FPGA cross-correlation exercise: a few-hundred-tap sliding dot product, or export the FIFO and correlate offline). Expected peak at lag 0: both mics sample on the same WS falling edge, so an equidistant source gives in-phase channels.
3. Move the source well off-axis toward one microphone. The correlation peak must shift by the acoustic path difference at roughly 2.9 us per mm (speed of sound 343 m/s); with the intended 10 cm spacing the endfire maximum is about 292 us, i.e. about 14 samples at 48 kHz.
4. Check the sign convention: source nearer U1 means the left channel leads. Record lag vs angle at a few positions; this is the calibration table a delay-and-sum beamformer demo will reuse.
5. Note the resolution limit honestly: at 48 kHz one sample is ~21 us, or about 7 mm of path difference, so fine angles need interpolated correlation or a higher sample rate (up to 51.6 kHz in HP mode).

F. Acoustic sanity and endurance (release-track, not first-power)#

1. In a quiet room, record noise-floor statistics and compare against the -90 dBFS A-weighted target (unweighted bench numbers will read higher; log the difference rather than fail on it).
2. If a calibrated 94 dB SPL source is available, verify -26 dBFS +/-1 dB sensitivity per channel; otherwise record relative L/R gain match only.
3. Soak with clocks running for an extended period, monitoring current; also verify clean recovery through stop-clocks/sleep/restart cycles.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a faithful implementation of the ICS-43434 datasheet's own stereo application circuit: disjoint hard-wired LR slots, tied SD pins, the recommended 100 kOhm pull-down, the required per-mic 0.1 uF decoupling, and the sensor-line 100 Ohm series rule on the one module-driven pin. The ERC-level modeling is unusually honest (the SD pin was re-typed to tri-state so the shared bus is checked, not waived). The principal risks are all downstream of the schematic: the unstarted layout (10 cm spacing, port keep-outs, decoupling placement, bus stub lengths against the 85 pF load limit), assembly quality around the acoustic ports, first-article LR strap verification, and re-verification of clock limits against datasheet v1.2. Until a fabricated board passes Sections 9.A-9.E, every number here remains a target.