← AXS-032

Circuit review & bench-test guide

AXS-032 — ADS1115 16-bit precision ADC PMOD module

Document purpose#

This document explains the axs-032-ads1115 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, and the TI ADS111x datasheet.

The board is a design-stage prototype. The schematic is generated and ERC clean (0 errors / 0 warnings) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended, I2C) module carrying a TI ADS1115 16-bit delta-sigma ADC: 4 single-ended / 2 differential inputs, an internal reference and oscillator, a PGA spanning ±0.256 V to ±6.144 V full scale, 8–860 SPS, and a comparator/conversion-ready output. AIN0–AIN3 plus a GND reference land on header J2 for breadboard use. SDA/SCL carry on-module 4.7 kΩ pull-ups (removable via solder jumpers JP1/JP2), ALERT/RDY has a 10 kΩ pull-up and reaches PMOD pin 1 through a 100 Ω series resistor, and solder jumper JP3 straps the I2C address to 0x48 (default) or 0x49.

It is the general-purpose precision analog input for the sensor line; it has no input protection network beyond the ADS1115's internal ESD diodes.

Functional block diagram#

PMOD J1                                   U1 ADS1115 (TSSOP-10)
 1 ADC_RDY <── R4 100R ── ADC_RDY_RAW <── ALERT/RDY (open drain)
                              └─ R3 10k pull-up to 3V3
 3/9  SCL ──┬── JP2 ── R2 4.7k ── 3V3    SCL
 4/10 SDA ──┴── JP1 ── R1 4.7k ── 3V3    SDA
 5/11 GND, 6/12 3V3 ── C1 100n ──────    VDD = 3V3, GND

 JP3: ADDR ── 1-2 GND (0x48, default) / 2-3 3V3 (0x49)
 J2: 1 AIN0, 2 AIN1, 3 AIN2, 4 AIN3, 5 GND

2. Safety and scope boundaries#

• Analog inputs must stay within GND − 0.3 V to VDD + 0.3 V regardless of the PGA setting. The ±6.144 V and ±4.096 V ranges only rescale the codes; they never make it safe to apply more than VDD + 0.3 V (datasheet Table 7-1 note and Section 5.1). On this 3.3 V module that means J2 inputs are limited to about −0.3 V to +3.6 V, hard.
• Never plug the module into a 5 V PMOD host; digital pins tolerate 5.5 V but the analog input limit follows VDD, and mixed-rail I2C invites back-powering through the pull-ups.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~50 mA; the ADC draws ~150 µA operating).
• Earth-referenced oscilloscope grounds clip only to board GND.
• Overdriving one input can corrupt conversions on the other inputs (datasheet Section 7.3.1); clamp externally if a source can exceed the window.
• A clean I2C readout is not a calibration or an accuracy certification; gain/offset specs apply at the chip level and this module is unverified.

3. Power and control sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11; C1 (100 nF) decouples VDD as the datasheet's typical application recommends.
2. The ADS1115 resets on power-up, loads Config = 0x8583, and enters power-down single-shot mode: it responds on I2C but converts nothing.
3. JP3 (bridged 1-2 by default) holds ADDR at GND, so the device answers at 7-bit address 0x48 (1001000b). ADDR is sampled continuously.
4. The host writes the Config register to select MUX, PGA, mode, and data rate; OS = 1 starts a single-shot conversion (device wakes in ~25 µs).
5. Results are read from the Conversion register as 16-bit two's complement. ALERT/RDY (open-drain, pulled up by R3) can signal comparator events or, with the threshold-register MSB trick, conversion-ready.
6. If the bus idles mid-transaction for more than 25 ms, the interface times out and the transaction must be restarted.

4. Interfaces and pin maps#

I2C address strap review (datasheet Table 7-2 vs this board):

So at most two AXS-032 modules can share one bus. JP1/JP2 must be cut on all but one module when chaining, or the parallel pull-ups get too stiff (two modules: 2.35 kΩ effective, still legal; more is marginal).

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

6. Datasheet summary and design interpretation#

Consulted: TI ADS1113/ADS1114/ADS1115 datasheet SBAS444E (May 2009 – revised December 2024), <https://www.ti.com/lit/ds/symlink/ads1115.pdf>, product page <https://www.ti.com/product/ADS1115>.

Check the latest datasheet revision before procurement.

7. Expected values before bench testing#

Targets assume VDD = 3.300 V, address 0x48, and the divider tests of Section 9.D built from 1% resistors. All are design targets, not measured results.

Divider-B codes scale with the actual rail and resistor values; compute the expected code as V_meas / LSB and compare within ±(0.2% + noise) as a sanity bound. Datasheet RMS noise at 128 SPS is a few µV — negligible next to resistor tolerance.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin 1 = ADDR) and the IDGSR suffix (TSSOP-10/DGS).
• Verify JP3 is bridged 1-2 (ADDR to GND) and pads 2-3 are open; confirm no three-pad bridge (would short 3V3 to GND).
• Verify JP1/JP2 are bridged for a single-module build.
• Measure R1/R2 = 4.7 k from SDA/SCL to 3V3, R3 = 10 k from ADC_RDY_RAW to 3V3, R4 = 100 Ω to PMOD pin 1.
• Buzz PMOD pins 3-to-9 (SCL) and 4-to-10 (SDA) — they are paired nets.
• Check C1 placement close to U1 pin 8 during layout review (layout not yet started — carry forward).
• Confirm no solder bridges on the 0.5 mm-pitch TSSOP, especially pins 9/10 (SDA/SCL).

Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, bus speed, measured VDD, and divider resistor values.

A. Unpowered inspection and resistance tests#

1. Complete the checklist above under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate < 1 kΩ.
3. Confirm SDA and SCL each read ~4.7 kΩ to 3V3 and are not shorted to each other or to GND.

B. First power, no I2C traffic#

Context (a) — PMOD host: plug into a 3.3 V PMOD port on the ECP5 host (ULX3S-class) with the FPGA unconfigured. Context (b) — standalone: wire 3V3/GND from a current-limited bench supply and SDA/SCL/ALERT to a 3.3 V lab adapter (Raspberry Pi Pico, FT2232H, Bus Pirate — I2C mode).

1. Supply current in the idle band; SDA, SCL, and ADC_RDY all sit at 3V3 (pull-ups working, nothing stuck low).
2. Measure VDD at U1 pin 8.

C. First transaction bring-up (exact bytes)#

Bus speed 100 kHz for bring-up. Address 0x48 means write byte 0x90 and read byte 0x91 on the wire.

1. Address scan / probe read. Read 2 bytes: S 0x91 [D15] [D7..D0] P. After power-up the pointer resets and the Conversion register reads 0x00 0x00. An ACK on 0x91 at all is the first pass criterion; NACK means address/JP3/solder trouble.
2. Config readback. Write the pointer only: S 0x90 0x01 P, then read two bytes: S 0x91 [MSB] [LSB] P. Expect the reset value 0x85 0x83.
3. First conversion. Write Config for a single-shot conversion of AIN0 vs GND, FSR ±4.096 V, 128 SPS, comparator disabled — bytes on the wire:

S 0x90 0x01 0xC3 0x83 P

(0xC3 = OS 1, MUX 100 = AIN0/GND, PGA 001 = ±4.096 V, MODE 1; 0x83 = DR 100 = 128 SPS, COMP_MODE 0, COMP_POL 0, COMP_LAT 0, COMP_QUE 11 = disabled.)

1. Wait >= 9 ms (1/128 s + margin), or poll Config until the MSB's OS bit reads 1 (0xC3 0x83 back; 0x43 0x83 while still converting).
2. Set the pointer to Conversion and read: S 0x90 0x00 P, then S 0x91 [MSB] [LSB] P. With Divider A on AIN0 expect ~0x33 0x90 (Section 7). With AIN0 grounded expect 0x0000 ± ~3 LSB (small negative values read as 0xFFxx — two's complement, not a fault).

D. PGA range walk with known dividers#

Build on a breadboard from J2: Divider A = 10.0k/10.0k (1%) from 3V3 to GND, tap to AIN0 (~1.650 V); Divider B = 33.0k/1.00k (1%) from 3V3 to GND, tap to AIN1 (~97.1 mV). Both taps are DMM-verified before trusting any code.

1. For each FSR, write Config MSB with the PGA bits set, single shot, MUX = AIN0 (0x4x/0xCx values below), LSB = 0x83, then read the result:

1. The Divider A clips are the teaching point: the code saturates cleanly because 1.65 V exceeds those FSRs, and this is only safe because 1.65 V is far below VDD + 0.3 V. Never demonstrate clipping with a voltage above the supply window.
2. Cross-check each unclipped code x LSB against the DMM reading of the tap. Note the finite input impedance (Section 6): Divider B's ~0.97 kΩ Thevenin impedance keeps loading error below ~0.15% even at the 710 kΩ differential-impedance ranges.

E. ALERT/RDY conversion-ready bring-up (exact bytes)#

Reset defaults (Lo = 0x8000, Hi = 0x7FFF) have the MSBs in the comparator orientation; RDY mode requires rewriting both thresholds.

1. Write Hi_thresh MSB = 1: S 0x90 0x03 0x80 0x00 P (Hi_thresh = 0x8000).
2. Write Lo_thresh MSB = 0: S 0x90 0x02 0x00 0x00 P (Lo_thresh = 0x0000).
3. Write Config for continuous conversion, AIN0, ±4.096 V, 128 SPS, COMP_QUE = 00 (assert after one conversion), COMP_POL = 1 (active-high pulse, matching datasheet Figure 7-8):

S 0x90 0x01 0xC2 0x88 P

(0xC2 = OS 1/ignored, MUX 100, PGA 001, MODE 0; 0x88 = DR 100, COMP_MODE 0, COMP_POL 1, COMP_LAT 0, COMP_QUE 00.)

1. Scope ADC_RDY (PMOD pin 1): expect an ~8 µs high pulse every ~7.8 ms (128 SPS). With COMP_POL = 0 (LSB 0x80) the pulse inverts: the line idles high through R3 and pulses low. In single-shot mode (MODE = 1) ALERT/RDY instead asserts at the end of each triggered conversion.
2. In the PMOD-host context, this is the interrupt line for the eventual HDL: verify the FPGA sees clean edges through R4 and that a conversion read always follows a pulse before the next one arrives.
3. Restore comparator-off defaults afterwards (Config LSB COMP_QUE = 11) or power-cycle.

F. Rate, chaining, and host-integration tests#

1. Repeat 9.D at 8 SPS and 860 SPS; codes must agree within the extra noise at 860 SPS (tens of µV RMS).
2. Two-module bus test (when two boards exist): one at 0x48, one strapped 0x49, JP1/JP2 cut on the second; scan must show both, and neither 0x4A nor 0x4B (not supported by this board's strap).
3. 400 kHz fast-mode regression of 9.C–9.E.
4. Temperature, EMC, and long-cable testing are out of scope for the first article.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a clean minimal application of the ADS1115: correct open-drain treatment of all three shared lines, cuttable pull-ups for multi-module buses, a two-position address strap that covers the two addresses reachable without routing ADDR to SDA/SCL, and series protection on the one line the ADC drives toward the host. The datasheet's central caution — that no PGA setting extends the safe input window beyond VDD + 0.3 V — is carried onto the schematic and must be carried into user documentation. The principal open risks are that no PCB exists yet (layout, input routing, and decoupling placement unverified), the total absence of input protection parts on J2 (deliberate, but it makes the input-window rule load-bearing), only two bus addresses being available, and the fact that every expected code in this guide is calculated from the datasheet rather than measured on hardware.