← AXS-034

Circuit review & bench-test guide

AXS-034 — INA219 current/power monitor PMOD module

Document purpose#

This document explains the axs-034-ina219 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic (generate_design.py, axs-034-ina219.kicad_sch), the module README, and the TI INA219 datasheet.

The board is schematic-only. ERC is clean (0/0) and the netlist has been reviewed, but no PCB layout exists, no board has been fabricated, and there is no recorded bench result of any kind. Every numeric value in this guide — register readbacks, calibration results, expected currents, resistances — is a verification target derived from the schematic and the datasheet, not a measured result. Treat nothing below as proof that an assembled board works.

1. What the board does#

The board is an I2C PMOD module around the TI INA219 high-side current, bus voltage, and power monitor. An external supply-and-load pair connects through J2; the load current flows through a 0.1 Ω 1 % 2 W shunt (R5) between J2 pin 1 (supply in) and J2 pin 2 (load out). The INA219 measures the shunt drop (±320 mV full scale at the default PGA = /8, i.e. 3.2 A with this shunt) and the bus voltage at IN− (0–26 V), and — once the calibration register is programmed — reports current and power directly over I2C.

The measured circuit must share ground with the PMOD host through J2 pin 3. The module teaches the INA219 calibration-register fixed-point exercise: choosing a Current_LSB, computing CAL, and interpreting the three data registers.

Functional block diagram#

 PMOD host J1                              measured circuit
 3V3/GND ────────┬──────────────┐
 SCL (3,9) ──┬───┼──> U1 SCL    │      supply in     load out
 SDA (4,10) ─┼─┬─┼──> U1 SDA    │      J2.1 ──> R5 0.1R ──> J2.2
             │ │ │              │        │VIN_P        VIN_M│
   R2 4.7k ──┘ │ │   INA219 U1 <┼────────┴──── IN+   IN− ───┘
   (via JP2)   │ │   VS=3V3     │        (kelvin sense pair)
   R1 4.7k ────┘ │   A0 <── JP3 (GND default / 3V3)
   (via JP1)     │   A1 <── JP4 (GND default / 3V3)
   C1 100n ──────┘
                     GND ── J2.3 (common ground reference)

2. Safety and scope boundaries#

• The INA219 supply (VS) comes from the PMOD 3V3 rail; the measured bus on J2 may be up to 26 V. Never confuse the two. Do not exceed 26 V on J2 pin 1 or 2 under any condition, including inductive kickback when breaking a load.
• The shunt inputs tolerate 26 V differential, but a load-side short places the full bus voltage across R5: at 26 V that is 6.76 kW demanded from a 2 W part. The shunt is not a fuse. Current-limit the measured supply.
• The measured supply's return must be tied to J2 pin 3 (module GND). Floating or dual-referenced grounds invalidate the bus-voltage reading and can drive pins outside absolute maximums.
• Use a current-limited 3.3 V bench supply (set ≈100 mA limit) or a real PMOD host for the logic side. The INA219 draws ≈1 mA maximum; anything more flowing into the 3V3 pin indicates a fault.
• This is a prototype without layout, DRC, fabrication, or bench history. Do not connect it to hardware you care about until the bring-up plan below has passed on a first article.
• Kelvin routing of the IN+/IN− sense traces is a layout requirement noted in the schematic but not yet realized; measurement accuracy claims are void until the layout exists and is reviewed.

3. Power and control sequence#

1. With no PMOD host attached, the board is unpowered. There is no local regulator; 3V3 and GND come straight from J1 (pins 6/12 and 5/11).
2. On power-up the INA219 performs a power-on reset (POR threshold 2 V) and loads its default configuration: register 0x00 = 0x399F (32 V bus range, PGA = /8 ±320 mV, 12-bit ADCs, continuous shunt-and-bus mode).
3. A0 and A1 are sampled on every bus transaction, not just at reset; JP3 (A0) and JP4 (A1) hold them at GND by default, giving 7-bit address 0x40.
4. Without calibration, the shunt-voltage (0x01) and bus-voltage (0x02) registers read real data immediately; current (0x04) and power (0x03) stay at zero until calibration register 0x05 is written.
5. The measured circuit on J2 is electrically independent of the logic supply sequence: the datasheet states the bus may be present with VS off and vice versa. No sequencing constraint exists between J1 and J2.

4. Interfaces#

PMOD pin map (Type 6 extended, J1)#

Pins 9/10 repeat the bus for module chaining; 11/12 repeat GND/3V3.

Load-path connector J2 (2.54 mm 1x03 header)#

Jumpers#

Address map reachable with these jumpers (INA219 Table 1):

The README's "0x40–0x45" span is only partly reachable: 0x42/0x43 require strapping A0 to SDA/SCL, which these jumpers do not offer. Honest limitation, not a defect.

Test points#

None are defined in the schematic. Probe at J1/J2 pins and the jumper pads. Adding TPs for VIN_P, VIN_M, SDA, SCL, and 3V3 is a recommended layout task.

5. Component-by-component review#

Every reference designator in generate_design.py is covered. Designators R3/R4 do not exist on this module (no gap-fill parts); the shunt is deliberately numbered R5.

5.1 Active device and connectors#

5.2 Shunt#

Note the 3.2 A ceiling: ±320 mV maximum PGA input ÷ 0.1 Ω. Beyond that the shunt register clips (out-of-range values shown shaded in datasheet Table 7) and the math-overflow flag (bus-voltage register bit 0, OVF) may assert.

5.3 Pull-ups, decoupling, and jumpers#

5.4 ERC-only artifacts#

6. Datasheet summary and design interpretation#

Official references: INA219 datasheet (SBOS448G), INA219 product page, Yageo RC thick-film resistors, Murata capacitor search. Check the latest datasheet revision before procurement.

Calibration-register math for this board (0.1 Ω shunt)#

Worked example — the values the HDL/driver should use and the bench should verify:

1. Maximum expected current: limited by the PGA to 320 mV / 0.1 Ω = 3.2 A.
2. Minimum Current_LSB = 3.2 A / 2^15 = 97.66 µA/bit. Round up to a friendly value: Current_LSB = 100 µA/bit.
3. CAL = trunc(0.04096 / (100 µA × 0.1 Ω)) = trunc(4096.0) = 4096 = 0x1000. Write 0x1000 to register 0x05.
4. Power_LSB = 20 × Current_LSB = 2 mW/bit.
5. Register interpretation:

• Shunt-voltage register 0x01: LSB = 10 µV, two's complement, sign-extended per PGA (at PGA/8, ±320 mV = ±32000 decimal).
• Bus-voltage register 0x02: shift right 3 bits, then LSB = 4 mV (13-bit value BD12..BD0); bit 1 = CNVR (conversion ready), bit 0 = OVF (math overflow).
• Current register 0x04 = Shunt reg × 4096 / 4096 = numerically equal to the shunt register with this CAL; multiply by 100 µA for amperes.
• Power register 0x03 = Current reg × Bus reg / 5000; multiply by 2 mW.

7. Expected values before bench testing#

All values are calculated targets, not measurements.

8. Manual schematic and assembly review checklist#

• Confirm U1 pin-1 orientation against the SOIC-8 pinout (A1 on pin 1; IN+ on pin 8 — the D-package pinout differs from SOT-23, check the right column).
• Verify R5 is the 0.1 Ω 2512 part, not a 0.1 kΩ or 0603 substitute; measure it in-circuit with a 4-wire milliohm setup if available (expect ≈0.10 Ω).
• Confirm JP1 and JP2 are bridged (default) or deliberately cut, matching the intended chain position. Exactly one side of JP3 and JP4 must be bridged.
• Verify C1 is placed at U1 VS (layout task: as close as possible).
• Buzz J1 pin 3 → U1 SCL, pin 4 → U1 SDA, and the 9/10 duplicates.
• Buzz J2 pin 1 → R5 → J2 pin 2, and J2 pin 1 → U1 IN+, J2 pin 2 → U1 IN− (kelvin pairs at layout).
• Confirm no solder short between VIN_P/VIN_M and 3V3 or GND: J2.1-to-GND and J2.2-to-GND should read open (megohms) on an unpowered board.
• Layout review (future): kelvin sense connections per datasheet section 11.1, shunt copper sized for 3.2 A, C1 adjacent to VS.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment, and raw data for every step. Assumed bench: PMOD host (3.3 V) or current-limited 3.3 V supply on J1, plus a second current-limited supply and a 33 Ω ≥1 W resistor for the load test.

A. Unpowered inspection and resistance tests#

1. Complete the checklist in section 8 under magnification.
2. Ohmmeter, unpowered: 3V3-to-GND at J1 — expect no hard short (>10 kΩ, settling as C1 charges from the meter).
3. SDA-to-3V3 and SCL-to-3V3: expect ≈4.7 kΩ each (R1/R2 through JP1/JP2). This is the standing JP1/JP2 verification: fitted = ≈4.7 kΩ, cut = open. Re-check after any jumper rework.
4. A0-to-GND and A1-to-GND at the JP3/JP4 center pads: expect ≈0 Ω (default 1-2 bridges).
5. J2.1-to-J2.2: expect ≈0.1 Ω (R5). J2.1-to-GND: open.

B. First power-up, logic side only#

1. Nothing on J2. Apply 3.3 V (current limit ≈100 mA) to J1 pins 6/12, GND to 5/11.
2. Supply current: expect ≈0.7–1 mA. Investigate >2 mA before proceeding.
3. DMM: SDA and SCL both read ≈3.3 V (bus idle high). A line stuck low means a solder short or damaged U1.

C. Address-ACK scan and first transaction#

1. Run an I2C scan at 100 kHz. Expected: ACK at 0x40 only (default straps). Any other ACK means a strap or address decode problem.
2. If JP3 is rebridged 2-3: expect 0x41. JP4 2-3: 0x44. Both: 0x45. Note 0x42/0x43 are unreachable on this board.
3. First transaction — config register readback: write pointer 0x00, then read 2 bytes:

• Bus bytes: S 0x40+W ACK 0x00 ACK Sr 0x40+R ACK 0x39 ACK 0x9F NACK P
• Expected data: 0x39 0x9F (POR default 0x399F).

1. Read 0x03, 0x04, 0x05: expect 0x0000 each (uncalibrated).
2. Optional: write 0x8000 to 0x00 (RST self-clearing bit), re-read 0x399F.

D. Calibration and zero-load sanity#

1. Write CAL: S 0x40+W 0x05 0x10 0x00 P. Read back 0x05: expect 0x1000.
2. With J2 still open, read 0x01 and 0x04: expect ≈0 (within a few LSB of offset; datasheet VOS at PGA/8 is ±200 µV max for the A grade, i.e. up to ±20 counts — record the actual zero offset for this serial).
3. Read 0x02: with nothing on J2, IN− floats; the bus reading is meaningless here. Do not fail the board on it.

E. Known-load current check#

1. Second supply: 3.3 V, current limit 150 mA, positive to J2.1, return to J2.3 (and commoned with J1 GND). Load: 33 Ω ≥1 W from J2.2 to J2.3.
2. Expected load current ≈ 3.3 / 33.1 ≈ 99.7 mA. Confirm on the supply readout or a series DMM.
3. Read the registers and compare:

• Shunt 0x01: ≈0x03E8 (1000 dec, 10.00 mV), accept 950–1050.
• Current 0x04: same count as 0x01 (CAL = 4096) → ≈100.0 mA.
• Bus 0x02: after >>3, ≈822 counts ≈ 3.29 V, accept 3.20–3.36 V.
• Power 0x03: ≈164 counts ≈ 328 mW, consistent with I×V within ±7 %.

1. Cross-check: DMM across R5 should read ≈10 mV and match the shunt register within tolerance. A ×2 or ×0.5 disagreement means the wrong shunt value or a broken kelvin connection.
2. Reverse test: swap supply and load (current flows J2.2 → J2.1). Shunt and current registers must go negative (two's complement, e.g. ≈0xFC18).

F. Range, overflow, and chaining tests (deferred/careful)#

1. Step the load toward higher currents only after the fabricated board's copper and shunt thermals are reviewed; verify OVF (0x02 bit 0) asserts past 3.2 A equivalent rather than silently wrapping. Do not soak at 3.2 A on a first article.
2. Chain test: two modules on one bus, one with JP1/JP2 cut; verify both addresses ACK and idle levels remain ≈3.3 V with the combined pull-up.
3. Bus-voltage range test with an elevated (e.g. 12 V) measured rail only after step E passes; confirm the 4 mV × count reading tracks a DMM.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a minimal, faithful implementation of the INA219 datasheet application circuit: shunt with kelvin intent, single 100 nF decoupler, strap-selectable address, and cuttable bus pull-ups for chaining. The calibration math closes cleanly for the 0.1 Ω shunt (Current_LSB = 100 µA, CAL = 0x1000, 3.2 A PGA-limited full scale). The principal open risks are exactly the unbuilt parts: no PCB layout (kelvin routing and shunt copper are still promises), no fabricated first article, and no bench evidence. The address-range claim in the README (0x40–0x45) should be trimmed to the four reachable codes, and the shunt-power ceiling (≈1 W dissipated at full scale) must be revisited during layout thermal review before any high-current use.