← AXS-037

Circuit review & bench-test guide

AXS-037 — Force sensitive resistor PMOD module

Document purpose#

This document explains the axs-037-fsr force-sensitive-resistor PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the manufacturer documents cited in section 6.

The board is a design-stage prototype: the schematic is generated and ERC is clean (0/0), but PCB layout has not started and no first article has been fabricated or assembled. Every voltage, resistance, and timing value below is a design target derived from calculation and typical manufacturer curves — a target to verify, not proof that a built board behaves this way. FSR curves in particular are typical data for one actuator setup; treat every numeric expectation in this guide as provisional until measured.

1. What the board does#

The board is a single-channel analog force-acquisition PMOD module. An Interlink FSR-402-class force sensing resistor (external, attached at J2) forms the upper leg of a resistive divider against a fixed 10 kΩ lower leg (R1). The divider node passes through a 1 kΩ / 10 nF anti-alias RC (R2/C1) into an ADS7042 12-bit 1 MSPS SAR ADC (U1), which is read over a chip-select framed, read-only SPI interface on a PMOD Type 2 connector (J1). AVDD = 3.3 V is also the ADC reference, so readings are ratiometric to the PMOD rail.

The output is deliberately nonlinear in force: the FSR resistance follows roughly an inverse power law with force, and the module's teaching goal is calibration (log-log fit or lookup table) in gateware/software, not a linear force scale.

Functional block diagram#

3V3 (PMOD pin 6/12)
  │
  ├──────────────┐
  │              │
FSR (external,   ├── C2 100 nF + C3 1 µF (AVDD/DVDD decoupling)
via J2 pins 1/2) │
  │              v
FSR_NODE ──> U1 ADS7042 (AVDD = reference = 3V3)
  │   \          │ SDO ── R3 100 Ω ── MISO (J1 pin 3)
R1 10k  R2 1k    │ SCLK <───────────── SCK (J1 pin 4)
  │       │      │ CS_N <── R4 10k pull-up to 3V3 ── ~CS (J1 pin 1)
 GND    ADC_IN   │ AINM ── GND
          │     GND
        C1 10nF
          │
         GND

2. Safety and scope boundaries#

• This is a 3.3 V logic-level module. It has no protection against supplies above 3.6 V: the ADS7042 absolute maximum AVDD/DVDD is 3.9 V and the recommended maximum is 3.6 V. Never plug it into a 5 V PMOD host or a bench supply set above 3.6 V.
• Do not drive AINP-side nets (FSR_NODE, ADC_IN) from an external source above AVDD + 0.3 V or below −0.3 V (ADS7042 absolute maxima).
• Interlink limits FSR current to 1 mA per cm² of applied force and pressure to below ~10 N/mm²; do not probe the FSR with a low-range ohmmeter that forces high current, and do not crush the sensor.
• The FSR is not waterproof and must not be soldered directly on its silver traces; use a clamped pin header, ZIF, or Amphenol/AMP-style clip at J2.
• FSRs are force indicators, not calibrated load cells. Interlink states system force accuracy ranges from approximately ±6% to ±50% depending on actuation consistency. Nothing in this guide produces a traceable force measurement.
• Working acquisition on the bench is not EMC, safety, or environmental qualification, and the module is marked NOT RELEASED.

3. Power and signal path#

1. The host (PMOD socket or bench supply) provides 3.3 V on J1 pins 6/12 and ground on pins 5/11. C3 (1 µF) and C2 (100 nF) decouple U1's shared AVDD/DVDD rail; AVDD is also the ADC reference.
2. With no FSR attached or no force applied, the FSR is effectively open (Interlink stand-off resistance spec: >10 MΩ unloaded, unbent), so R1 holds FSR_NODE essentially at 0 V.
3. Applied force lowers R_FSR; the divider output rises according to V_node = 3.3 V × 10 kΩ / (10 kΩ + R_FSR).
4. R2 (1 kΩ) and C1 (10 nF) form a ~15.9 kHz low-pass anti-alias filter and give the SAR input a local charge reservoir; at DC the ADC input tracks FSR_NODE (input leakage only).
5. R4 (10 kΩ) holds CS_N high so U1 stays deselected (SDO released) until the host drives ~CS low. Each ~CS-framed 16-SCLK burst returns one 12-bit sample (leading zeros then data); SDO reaches the host MISO through R3.
6. Code ≈ 4095 × V_node / 3.3 V. Because AVDD is the reference, rail error cancels to first order for a ratiometric divider driven from the same rail — one reason the FSR is tied to 3V3 rather than a separate source.

4. Interfaces and usage contexts#

The bench plan covers two usage contexts; every powered test states which applies:

• Context A — PMOD host: plugged into a 3.3 V PMOD socket on an ECP5-class FPGA board (e.g., ULX3S). The FPGA drives ~CS/SCK and reads MISO; supply current limiting is whatever the host provides.
• Context B — standalone bench: powered from a current-limited bench supply (3.30 V, ≤50 mA limit) on pins 6/12 and 5/11, with the divider observed by DMM/scope and SPI driven by a lab MCU or USB SPI adapter (3.3 V logic only). Context B is the safer place for first power-up.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag directives on 3V3 and GND, not physical parts.

5.1 Sensing and acquisition path#

5.2 Digital interface and decoupling#

6. Datasheet summary and design interpretation#

Official references actually consulted: Interlink FSR 400 Series Integration Guide (Rev. C, 94-00004), Pololu mirror (also hosted by Digi-Key); Interlink FSR 402 product page; TI ADS7042 datasheet (SBAS608C). Check the latest revision before procurement; the FSR MPN is still TBD (FSR-402 vs Ohmite FSR01CE per the README), and the two are not curve-identical.

7. Expected values before bench testing#

Divider formula for this board (FSR is the upper leg, R1 = 10 kΩ lower leg):

V_node = 3.3 V × 10 kΩ / (10 kΩ + R_FSR)        code ≈ 4095 × V_node / 3.3 V
R_FSR  = 10 kΩ × (3.3 V − V_node) / V_node       (inverse, for calibration)

Resistance points below come from the integration guide's Figure 3 (model 402, 4 mm silicone actuator) and its FAQ/spec tables. They are typical values for one specific setup; expect large deviations with a finger.

Other measurable design targets:

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation and the DCU (VSSOP-8) pin map: AVDD pin 7, GND pin 8, AINP pin 6 to ADC_IN, AINM pin 5 to GND, ~CS pin 4, SCLK pin 2, SDO pin 3, DVDD pin 1. A one-pin rotation is fatal.
• Measure R1 (10 kΩ 1%), R2 (1 kΩ), R3 (100 Ω), R4 (10 kΩ) in place before first power (power off, FSR disconnected).
• Confirm C1 is C0G, not an X7R substitute, and C2/C3 are populated close to U1 (layout review item once layout exists).
• Confirm J2 pin 1 goes to 3V3 and pin 2 to FSR_NODE; label the header.
• Confirm PMOD pin 1 is ~CS and pin 3 is MISO at the connector, not mirrored; a mirrored plug maps power to signals on some hosts.
• Inspect the FSR tail: no kinks/creases (bend radius ≥2.5 mm), no solder directly on silver traces, vent not blocked, sensor flat on a smooth surface with no trapped bubbles under any adhesive (all Interlink "do's and don'ts").

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, FSR unit identity (they differ part-to-part), actuator used, equipment IDs, ambient, operator.

A. Unpowered inspection and resistance tests#

1. Complete the checklist in section 8 under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate any hard short before power.
3. With the FSR unattached, measure it standalone on a DMM high-ohms range: expect overrange/>10 MΩ unloaded and a smooth drop into the 100 kΩ-to-kΩ region with increasing finger pressure. A sensor that reads low unloaded is pre-loaded (mounting/bend) or damaged.
4. Verify FSR_NODE-to-GND reads ≈10 kΩ (R1) with the FSR off the board.

B. First power-up, standalone (context B)#

1. Bench supply 3.30 V, current limit 50 mA, to J1 pins 6/12 (3V3) and 5/11 (GND). No SPI master, no FSR yet.
2. Confirm supply current is in the sub-mA range and nothing warms.
3. FSR_NODE and ADC_IN should read <10 mV (only leakage across R1).
4. Attach the FSR at J2. Unloaded readings should stay <10 mV; if the node sits noticeably above that, the sensor is pre-loaded or mis-mounted.

C. Static divider and force progression (context B)#

1. DMM on ADC_IN. Apply a slow finger-press progression: no touch, light touch, moderate, firm, hard. Expect the section 7 monotonic staircase: ~0 V → ~0.3 V (threshold) → 1–2 V (moderate) → 2.5–3.0 V (hard).
2. For semi-quantitative points, use known masses on a flat puck covering the active area (do not bridge the perimeter adhesive; do not exceed ~10 N/mm²). Log V_node at each mass, compute R_FSR with the inverse formula, and compare to the section 7 table — deviations of tens of percent are normal and are the calibration lesson, not a fault.
3. Hold a constant mass for 60 s and log V_node vs time: expect upward resistance-settling/drift behavior on the order of seconds mechanically plus slow drift (guide: <5%/log10(time)). Note it; do not "fix" it.
4. Release and repeat the same mass 5 times: single-part repeatability should be in the few-percent range only if the actuation is mechanically repeatable; finger presses will not be.

D. SPI acquisition#

1. Context B first (lab MCU / USB SPI adapter, 3.3 V logic): idle ~CS high (verify R4 holds it high when the adapter tri-states). Run ~CS-framed 16-SCLK reads at ≤1 MHz SCLK initially; expect frames of leading zeros then a 12-bit code matching the DMM voltage within a few LSB-equivalent millivolts. Sweep SCLK upward (ADS7042 supports up to 16 MHz) and confirm codes do not shift.
2. Scope ~CS, SCK, MISO on the first frames; check R3 keeps edges clean and that SDO releases when ~CS is high.
3. Context A (ULX3S-class PMOD host): with the same FSR and actuator, run the FPGA sampler and compare codes against the context-B baseline at the same three force levels. Differences beyond noise implicate rail level (measure the host's actual 3V3), grounding, or gateware framing.
4. In context A, verify the host pin constraints: pin 1 = ~CS, 3 = MISO, 4 = SCK, and that no host pull-down overrides R4 at configuration time.

E. Repeatability, drift, and calibration data set#

1. Collect a calibration table (mass vs mean code, N ≥ 5 presses per mass, consistent actuator) in the intended final mounting.
2. Log a 30–60 minute static-load run for drift characterization.
3. Fit log(force) vs log(R_FSR) or build the LUT; record fit residuals as the honest accuracy statement for this specific sensor unit.

F. Release-only tests#

Layout-dependent verification (decoupling placement, trace routing near the divider), temperature/humidity behavior (Interlink: humidity is the largest environmental effect; −15% R at 85 °C hot operation), long-term actuation endurance, and the design-review checklist in the README all remain open until a fabricated first article exists.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is minimal and coherent: a ratiometric FSR divider, properly isolated and filtered into a reference-shared SAR ADC, with the only digital risks being ~CS idling (covered by R4) and SDO integrity (covered by R3). The 10 kΩ R1 is a defensible mid-range measuring-resistor choice per Interlink's guidance, centering sensitivity on light-to-moderate presses; anyone wanting firm-press resolution should consider a smaller R1 and re-derive section 7. The principal open risks are that no board has been fabricated (layout, decoupling placement, and the sense-trace environment are all unverified), the FSR MPN is unpinned, and every expected value in section 7 rests on typical single-actuator curves that Interlink itself labels reference-only — part-to-part and actuation-dependent errors of ±25% or worse must be assumed until this specific sensor is calibrated in its final mounting.