← AXS-038

Circuit review & bench-test guide

AXS-038 — TTP223 capacitive-touch PMOD module

Document purpose#

This document explains the axs-038-touch capacitive-touch PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the Tontek datasheet cited in section 6.

The board is a design-stage prototype: the schematic is generated and ERC is clean (0/0), but PCB layout has not started and no first article has been fabricated or assembled. Capacitive-touch behavior is dominated by layout, electrode geometry, and overlay — exactly the things that do not exist yet — so every threshold, timing, and sensitivity statement below is a design target to verify, not proof of behavior. The consulted TTP223-BA6 datasheet is itself marked "Preliminary" (V2.1), and the datasheet URL embedded in generate_design.py currently returns 404; both facts are flagged honestly in section 6.

1. What the board does#

The board is the simplest sensor in the AruviX line: a Tontek TTP223-BA6 single-key capacitive touch detector (U1) whose debounced output Q drives one PMOD GPIO (TOUCH, J1 pin 1) through a 100 Ω series resistor (R1). The sense electrode attaches at J2 (a 1×1 pin-header pad on net TOUCH_PAD, wired to U1 pin 3). A DNP capacitor C2 (10 pF placeholder, 0–50 pF usable) desensitizes the input when fitted. Two open solder jumpers strap the TTP223's power-on-sampled option pins to 3V3: JP1 → AHLB (output polarity) and JP2 → TOG (momentary vs toggle). Both pins have internal pull-downs, so the open-jumper default is momentary, active-high output.

The teaching goals are FPGA input synchronizers, debouncing, edge detection, and toggle logic — plus, on the hardware side, what a capacitive electrode actually is.

Functional block diagram#

3V3 (J1 pin 6/12) ──┬── C1 100 nF ── GND
                    │
                    v VDD (pin 5)
J2 TOUCH PAD ──── I (pin 3)  U1 TTP223-BA6  Q (pin 1) ── R1 100 Ω ── TOUCH (J1 pin 1)
      │                        AHLB (pin 4) ──[JP1 open]── 3V3
   C2 10 pF (DNP)              TOG  (pin 6) ──[JP2 open]── 3V3
      │                        VSS  (pin 2) ── GND
     GND            (AHLB/TOG have internal ~28 kΩ pull-downs,
                     sampled/latched at power-on)

2. Safety and scope boundaries#

• 3.3 V logic module. The TTP223 itself tolerates 2.0–5.5 V, but the PMOD contract and any host it plugs into are 3.3 V; never mix a 5 V-powered module with a 3.3 V host input.
• Do not drive the TOUCH net from the host: Q is a CMOS push-pull output. R1 limits contention current but is not a license to fight the pin (sink/source capability is only ~8 mA/−4 mA at 3 V).
• The sense input I is a high-impedance pin with ESD rating 4 kV HBM at the chip; a long unshielded electrode wire is still an ESD and EMI antenna. Handle with grounding discipline and keep test wiring short.
• Touch detection here is a human-interface convenience, not a safety interlock. Do not use it to gate anything hazardous.
• Bench results with a hand-soldered electrode do not transfer to the final layout: trace length, ground pour proximity, and overlay all change the baseline capacitance and therefore the sensitivity and calibration.
• Working detection is not EMC/ESD qualification, and the module is marked NOT RELEASED.

3. Power and control sequence#

1. The host (PMOD socket or bench supply) provides 3.3 V/GND; C1 decouples U1 VDD locally.
2. At power-on, U1 latches AHLB and TOG (internal pull-downs read 0 unless the corresponding jumper is bridged to 3V3), then runs a ~0.5 s stabilization during which it calibrates its no-touch baseline and detection is disabled. Per the datasheet: "After power-on have about 0.5sec stable-time, during the time do not touch the key pad." Touching (or holding) the electrode during this window is captured into the baseline and mis-calibrates the key.
3. In idle the device sits in low-power mode (typ 1.5 µA at 3 V), waking ~every 160 ms to sample. A detected touch switches it to fast mode; after release it stays in fast mode for ~12 s before returning to low-power mode.
4. Auto-recalibration runs for life: in low-power mode the re-calibration period is about 4.0 s; after a touch is detected and released, re-calibration resumes about 16 s after release. Slow environmental drift (humidity, temperature) is absorbed; a permanently-present "touch" is eventually calibrated out.
5. Q drives the latched mode's output through R1 to the host. Response time is max 220 ms in low-power mode and max 60 ms in fast mode (both at VDD = 3 V), so the first touch after idle can take up to ~220 ms while repeated touches respond faster.

4. Interfaces, jumpers, and usage contexts#

Mode-jumper truth table (per datasheet output-mode table)#

Notes: on the BA6 variant Q is CMOS push-pull in all four modes; open-drain outputs exist only on other TTP223 family variants (pad/bonding options), so do not expect wired-OR behavior from this part. The option pins are latch-type: strapping them to 3V3 through a jumper causes no static current per the datasheet, and changes take effect only at the next power-on — re-jumpering a powered board does nothing until power cycles.

The bench plan covers two usage contexts; every powered test states which applies:

• Context A — PMOD host: plugged into a 3.3 V PMOD socket on an ECP5-class FPGA board (e.g., ULX3S), with the FPGA sampling TOUCH through a 2-FF synchronizer.
• Context B — standalone bench: 3.30 V current-limited bench supply (≤20 mA) on J1 pins 6/12 and 5/11, TOUCH observed on a DMM/scope or a lab MCU input. Context B is the right place for first power-up and for all sensitivity/electrode experiments, because power cycling (needed for every jumper change and calibration reset) is trivial.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag directives on 3V3 and GND, not physical parts.

6. Datasheet summary and design interpretation#

Sources actually consulted: TTP223-BA6/TTP223N-BA6 datasheet V2.1 (Components101 mirror) and the LCSC-hosted copy. The Tontek URL recorded in generate_design.py (https://www.tontek.com.tw/uploads/product/106/TTP223-BA6_V1.0_EN.pdf) returned 404 at review time and references an older V1.0 — update the schematic Datasheet field to a live link before release.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation on the SOT-23-6 pads: 1 Q, 2 VSS, 3 I, 4 AHLB, 5 VDD, 6 TOG (per datasheet pad description). Verify the marking is "223B" (BA6), not "223NB" (N variant).
• Verify with an ohmmeter (power off) that both JP1 and JP2 are open for the default build: AHLB-to-3V3 and TOG-to-3V3 must not read short, and AHLB/TOG-to-GND should show the internal pull-down (~28 kΩ class, in-circuit reading may differ).
• Confirm C2 is not populated for the default build; if a build variant fits it, confirm C0G/NPO dielectric and value ≤50 pF.
• Confirm C1 is present and (at layout review) tight to U1 pins 5/2.
• Confirm J2 lands on U1 pin 3 and that the sense net does not touch GND.
• Confirm PMOD pin 1 = TOUCH, pins 5/11 = GND, 6/12 = 3V3 at the connector.
• Layout review (when layout exists): sense trace short, not parallel to or crossing the PMOD bus, no ground pour directly under the electrode unless the sensitivity budget accounts for it, no metal in any overlay.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Every jumper or Cs change requires a power cycle (option pins latch at power-on; calibration baseline is also rebuilt then). Keep hands clear of the electrode for ~1 s at each power-up.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure 3V3-to-GND in both polarities; investigate hard shorts first.
3. Measure TOUCH_PAD-to-GND: should be high impedance (no C2, no bridge).
4. Verify JP1/JP2 open and record AHLB/TOG-to-GND readings.

B. First power-up and default-mode check (context B)#

1. Bench supply 3.30 V, 20 mA limit. Power up with nothing near J2.
2. After the ~0.5 s stabilization, TOUCH must idle low. Record idle supply current after ≥12 s (fast-mode hold expiry); expect µA-class.
3. Touch the J2 pin (or a small attached pad) firmly: TOUCH goes high for the duration of the touch and returns low on release — momentary, active-high. Latency up to ~220 ms on the first touch is normal.
4. Repeat several touches; within ~12 s of activity responses should feel near-instant (≤60 ms).

C. Power-on calibration behavior (context B)#

1. Power off. Hold a finger on the electrode, power on, keep holding ~2 s, then release. Expected mis-calibration signature: the touch present at power-up is baked into the baseline, so it is not reported, and behavior immediately after release may be inverted or dead.
2. Hands off, wait and observe: auto-recalibration (~4 s period idle, ~16 s after a release event) should restore normal behavior without a power cycle. Record how long recovery actually takes.
3. Power cycle cleanly (hands off) and confirm normal behavior returns immediately after the 0.5 s window.
4. Slow-drift check: rest a grounded metal object near (not touching) the electrode for >30 s — the device should calibrate it out; removing it may cause a brief anomaly that self-heals within the recal period.

D. Sensitivity (Cs) tuning ladder (context B)#

Per the datasheet, sensitivity depends on electrode size, overlay/panel thickness, and Cs; only Cs is tuned here, 0–50 pF, larger = less sensitive.

1. Start at the board default: C2 DNP (0 pF, maximum sensitivity) with the intended electrode attached. Characterize: minimum finger pressure/area for detection, detection-through-overlay (add plastic sheets of known thickness), and false-trigger behavior when a hand hovers.
2. If the key is too sensitive (hover-triggers, or cabled electrode false-fires): power off, fit C0G/NPO capacitance at C2, power on hands off, re-test. Suggested ladder: 5 pF → 10 pF (board's placeholder value) → 22 pF → 33 pF → 47 pF. Stay ≤50 pF.
3. At each step record: fitted Cs, detects-firm-touch (Y/N), detects-light-touch (Y/N), hover false-trigger (Y/N), works through intended overlay (Y/N). Choose the smallest Cs that kills false triggers while keeping the intended press reliable.
4. If even 47 pF is too sensitive, the electrode is too large or the wire too long — fix the electrode, not the capacitor.

E. Electrode (pad-wire) experiments (context B)#

1. Wire length: attach 5 cm, 20 cm, 50 cm wires to J2 with a 15 mm foil pad at the end. Longer wire = more baseline capacitance and more pickup: expect reduced margin and eventually false triggers; note where each configuration lands and whether Cs re-tuning is needed (every change: power cycle, hands off).
2. Ground proximity: run the electrode wire flat against a grounded plane vs suspended in air. Adjacent ground raises baseline capacitance (less sensitive) but improves noise immunity — record both effects.
3. Overlay thickness: stack 1–5 mm of plastic/glass (no metal — the datasheet forbids metal or conductive paint in the panel) over the foil pad; find the thickness where a firm press stops being detected at the chosen Cs. Thinner panel = more sensitive.
4. Record the final chosen electrode/Cs combination as the layout requirement for the shipped board (README open item: on-board copper pad vs J2 wire).

F. Mode-jumper matrix and host integration#

1. Context B, all four jumper combinations (power off, re-solder, power on hands off, test, record): verify each row of the section 4 truth table — default momentary active-high; JP1 only → momentary active-low (idle high); JP2 only → toggle starting low; both → toggle starting high. Confirm a jumper change while powered has no effect until the next power cycle.
2. Context A (ULX3S-class PMOD host): with the chosen electrode and mode, run the FPGA design (2-FF synchronizer, debounce, edge detect). Confirm clean single events per touch, no double-edges, and that FPGA configuration-time pin states do not disturb the module (TOUCH is module-driven; the host pin must be a plain input, no pull fighting R1).
3. In context A, repeat a power-on-while-touched test — the host powers the module at configuration time, so a user resting a finger on the pad during board power-up is the realistic mis-calibration scenario. Verify self-recovery.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is a faithful minimal implementation of the datasheet's application circuit: decoupled TTP223-BA6, high-impedance electrode node with an optional 0–50 pF trim, series-protected CMOS output, and latch-type option straps correctly drawn as passive jumpers to 3V3 against the internal pull-downs. The design decisions that matter — electrode geometry, sense trace routing, overlay, and the final Cs value — are all deferred to layout and bench tuning, which is appropriate but means essentially nothing about real-world sensitivity is verified today. The principal open risks are: no fabricated first article; a dead datasheet URL in the generator (and a "Preliminary"-status datasheet generally); the unresolved on-board-pad vs wire electrode decision; the variant-dependent, unverified maximum-on-time behavior; and the human-factors trap that both mode changes and calibration are power-on events — a lesson the bench plan makes explicit rather than hides.