Sensor modules

AXS-046 — GPS/GNSS carrier PMOD module

Catalog #46 in the AruviX sensor line, level L3 (UART, NMEA parsing, PPS timing).

Level L3 ERC clean DRC clean Fab package 6 components

3D render of the AXS-046 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Socket decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Acquisition-current bulk reservoir at the GPS socket	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	GPS BREAKOUT SOCKET	Socket for a 3.3 V UART GPS breakout with PPS	not selected generic	`PinSocket_1x05_P2.54mm_Vertical`
`R1`	100R	Series protection on the module-driven UART TX line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection on the module-driven PPS line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 GND GPS_PPS GPS_TX PPS RXD TXD

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-046-gps

Catalog #46 in the AruviX sensor line (../README.md), level L3 (UART, NMEA parsing, PPS timing).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

A UART receiver in fabric, streaming NMEA sentence parsing (a nice character-FSM exercise), and using the 1 Hz PPS edge as a precision time reference — e.g. disciplining a fabric counter against it.

Design#

This is a carrier for a 3.3 V GPS breakout (ATGM336H-class) on a 1×5 socket: 3V3 / RX / TX / PPS / GND. Breakout pin orders vary — check against the J2 silkscreen before plugging in. A fully SMT carrier with the castellated ATGM336H footprint is deferred until that footprint is verified against the vendor drawing.

100 Ω series on the module-driven TX and PPS lines.
10 µF reservoir for acquisition current at the socket.
TXD/RXD are named from the host FPGA's viewpoint; PPS rides in the PMOD Type 3 CTS position (pin 1).

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	PPS	TXD	RXD	NC	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (20 × 40 mm outline — socket + antenna clearance), DRC, fab
[ ] hdl/: UART RX core, NMEA parser, PPS-disciplined counter, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist